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MC100EL15 PDF预览

MC100EL15

更新时间: 2024-11-19 22:46:23
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
4页 92K
描述
1:4 Clock Distribution Chip

MC100EL15 数据手册

 浏览型号MC100EL15的Datasheet PDF文件第2页浏览型号MC100EL15的Datasheet PDF文件第3页浏览型号MC100EL15的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10EL/100EL15 is a low skew 1:4 clock distribution chip  
designed explicitly for low skew clock distribution applications. The  
device can be driven by either a differential or single-ended ECL or, if  
positive power supplies are used, PECL input signal. If a single-ended  
input is to be used the V  
output should be connected to the CLK input  
and bypassed to ground via a 0.01µF capacitor. The V output is  
BB  
BB  
designed to act as the switching reference for the input of the EL15 under  
single-ended input conditions, as a result this pin can only source/sink up  
to 0.5mA of current.  
The EL15 features a multiplexed clock input to allow for the distribution  
of a lower speed scan or test clock along with the high speed system  
clock. When LOW (or left open and pulled LOW by the input pulldown  
resistor) the SEL pin will select the differential clock input.  
16  
1
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751B-05  
The common enable (EN) is synchronous so that the outputs will only  
be enabled/disabled when they are already in the LOW state. This avoids  
any chance of generating a runt clock pulse when the device is  
enabled/disabled as can happen with an asynchronous control. The  
internal flip flop is clocked on the falling edge of the input clock, therefore  
all associated specification limits are referenced to the negative edge of  
the clock input.  
50ps Output-to-Output Skew  
Synchronous Enable/Disable  
Multiplexed Clock Input  
PIN DESCRIPTION  
75kInternal Input Pulldown Resistors  
>1000V ESD Protection  
PIN  
FUNCTION  
CLK  
SCLK  
EN  
Diff Clock Inputs  
Scan Clock Input  
Sync Enable  
Clock Select Input  
Reference Output  
Diff Clock Outputs  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
SEL  
V
Q
BB  
0–3  
V
EN SCLK CLK CLK  
V
SEL  
10  
V
EE  
CC  
BB  
FUNCTION TABLE  
16  
15  
14  
13  
12  
11  
9
CLK  
SCLK  
SEL  
EN  
Q
1
0
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*  
D
Q
* On next negative transition of  
CLK or SCLK  
1
2
3
4
5
6
7
8
Q0  
Q0  
Q1  
Q1  
Q2  
Q2  
Q3  
Q3  
5/95  
Motorola, Inc. 1996  
REV 2  

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