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MC100E1651FN PDF预览

MC100E1651FN

更新时间: 2024-09-30 22:46:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 比较器输出元件
页数 文件大小 规格书
7页 137K
描述
DUAL ECL OUTPUT COMPARATOR WITH LATCH

MC100E1651FN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10E1651 is functionally and pin-for-pin compatible with the  
MC1651 in the MECL III family, but is fabricated using Motorola’s  
advanced MOSAIC III process. The MC10E1651 incorporates a fixed  
level of input hysteresis as well as output compatibility with 10KH logic  
devices. In addition, a latch is available allowing a sample and hold  
function to be performed. The device is available in both a 16-pin DIP and  
a 20-pin surface mount package.  
DUAL ECL OUTPUT  
COMPARATOR  
WITH LATCH  
The latch enable (LEN and LEN ) input pins operate from standard  
a
b
ECL 10KH logic levels. When the latch enable is at a logic high level the  
MC10E1651 acts as a comparator, hence Q will be at a logic high level if  
V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When  
the latch enable input goes to a low logic level, the outputs are latched in  
their present state providing the latch enable setup and hold time  
constraints are met.  
Typ. 3.0 dB Bandwidth > 1.0 GHz  
Typ. V to Q Propagation Delay of 775 ps  
Typ. Output Rise/Fall of 350 ps  
Common Mode Range –2.0 V to +3.0 V  
Individual Latch Enables  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 775-02  
Differential Outputs  
28mV Input Hysteresis  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620-10  
LOGIC DIAGRAM  
V1a  
FUNCTION TABLE  
Qa  
V2a  
LEN  
V1, V2  
Function  
H
H
L
V1 > V2  
V1 < V2  
X
H
L
LEN  
Qa  
a
Latched  
V1b  
V2b  
Qb  
Qb  
LEN  
b
V
V
= –5.2 V  
= +5.0 V  
EE  
CC  
12/93  
Motorola, Inc. 1996  
REV 1  

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