AvnetCore: Datasheet
Version 1.0, July 2006
UTOPIA Level 3 PHY
Intended Use:
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ATM Cell Processors
PHY Processors
ATM Bridges & Gaskets
DSL ASSP interfaces
UNI/MAC
Microprocessor interfaces
Features:
top_slave
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Function compatible with ATM Forum af-phy-0136.000
top_egr_slave
Asynchronous/synchronous FIFO using RAM
Up to 256 PHY ports supported
8/16/32 bit interfaces supported
Direct and polled status
TxClk
TxData
TxEnb_n
TxClav
TxSoc
rd_data
rd_enb
rd_clk
wr_data
wr_enb
a_full
fifo_16 / fifo_8
tx_utopia3_slave
rd_flag
TxPrty
TxAddr
Simple system side FIFO interface
Flow control and polling integrated
reset_n
top_ing_slave
Targeted Devices:
RxClk
RxData
RxEnb_n
RxClav
wr_data
wr_flag
wr_enb
wr_clk
®
rd_data
rd_enb
rd_flag
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Axcelerator Family
fifo_16 / fifo_8
rx_utopia3_slave
®
RxPrty
ProASIC 3 Family
RxSoc
PLUS®
RxAddr
ProASIC
Family
Core Deliverables:
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Netlist Version
> Compiled RTL simulation model, compliant with the Actel
®
Libero environment
> Netlist compatible with the Actel Designer place and route tool
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RTL Version
> VHDL Source Code
All
Block Diagram
> User Guide
> Test Bench
UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 3 defines the
interface between the ATM or LINK layer and a Physical Layer (PHY) device. The
UTOPIA Level 3 standard defines a full duplex interface with a Master/Slave format.
The Slave or LINK layer device responds to the requests from the PHY or Master
device. The Master performs PHY arbitration and initiates data transfers to and from
the Slave. The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in
width, at up to 104 MHz, supporting an OC48 channel at 2.5 Gbps.
Synthesis and Simulation Support:
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Synthesis: Synplicity
®
Simulation: ModelSim
Other tools supported upon request
Verification:
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Test Bench
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Test Vectors