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MC-ACT-UL3LINK-NET

更新时间： 2024-02-29 08:09:07

品牌	Logo	应用领域
ACTEL		现场可编程门阵列可编程逻辑先进先出芯片异步传输模式 ATM
页数	文件大小	规格书
5页	271K
描述
Function compatible with ATM Forum Asynchronous/synchronous FIFO using RAM

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技术参数
数据手册

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MC-ACT-UL3LINK-NET 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.82
JESD-30 代码：	R-XXMA-X	封装主体材料：	UNSPECIFIED
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
表面贴装：	NO	端子形式：	UNSPECIFIED
端子位置：	UNSPECIFIED	Base Number Matches：	1

MC-ACT-UL3LINK-NET 数据手册

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AvnetCore: Datasheet

Version 1.0, July 2006

UTOPIA Level 3 Link

Intended Use:

—

Cell Processors

Switch Fabrics

Networking

Telecommunications

top_master.vhd

Features:

top_egr_master.vhd

—

Function compatible with ATM Forum

wr_enb

wr_data

wr_flag

wr_clk

rd_enb

rd_data

rd_flag

txclk

tx_data

txenb_n

txclav

tx_soc

txprty

Asynchronous/synchronous FIFO using RAM

Up to 256 phys supported

8/16/32 bit interfaces supported

Simple system side FIFO interface

Flow control and polling integrated

fifo_16.vhd/fifo_8.vhd

egr_utopia_master.vhd

tx_addr

reset_n

Targeted Devices:

top_ing_master.vhd

—

Axcelerator Family

rd_enb

rd_data

rd_flag

rd_clk

wr_enb

wr_data

wr_flag

rxclk

rxdata

Core Deliverables:

rxenb_n

rx_clav

rx_prty

rx_soc

rx_addr

fifo_16.vhd/fifo_8.vhd

ing_utopia_master.vhd

—

Netlist Version

> Netlist compatible with the Actel Designer place and route tool

> Compiled RTL simulation model, compliant with the Actel

increment

Libero environment

—

RTL Version

> VHDL Source Code

All

> User Guide

> Test Bench

Block Diagram

Synthesis and Simulation Support:

—

Synthesis: Synplicity

UTOPIA (Universal Test and Operations PHY Interface for ATM) level 3 defines the

interface between the ATM or LINK layer and a Physical Layer (PHY) device. The

UTOPIA level 3 standard defines a full duplex interface with a Master/Slave format. The

Slave or LINK layer device responds to the requests from the PHY or Master device.

The Master performs PHY arbitration and initiates data transfers to and from the Slave.

The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in width, at up to

104 MHz, supporting an OC48 channel at 2.5 Gbps.

Simulation: ModelSim

Other tools supported upon request

Verification:

—

Test Bench

—

Test Vectors

12 3 4 5

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