Datasheet > MC-ACT-SDRAMDDR-NET

MC-ACT-SDRAMDDR-NET

更新时间： 2024-11-09 11:11:11

品牌	Logo	应用领域
ACTEL		动态存储器双倍数据速率控制器
页数	文件大小	规格书
5页	291K
描述
Double Data Rate SDRAM Controller

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MC-ACT-SDRAMDDR-NET 技术参数

生命周期：	Transferred	包装说明：	MODULE PACKGE
Reach Compliance Code：	unknown	风险等级：	5.62
JESD-30 代码：	R-XXMA-X	封装主体材料：	UNSPECIFIED
封装形状：	UNSPECIFIED	封装形式：	MICROELECTRONIC ASSEMBLY
认证状态：	Not Qualified	表面贴装：	NO
技术：	CMOS	端子形式：	UNSPECIFIED
端子位置：	UNSPECIFIED	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

MC-ACT-SDRAMDDR-NET 数据手册

浏览型号MC-ACT-SDRAMDDR-NET的Datasheet PDF文件第2页

浏览型号MC-ACT-SDRAMDDR-NET的Datasheet PDF文件第3页

浏览型号MC-ACT-SDRAMDDR-NET的Datasheet PDF文件第4页

浏览型号MC-ACT-SDRAMDDR-NET的Datasheet PDF文件第5页

AvnetCore: Datasheet

Version 1.0, July 2006

Double Data Rate

SDRAM Controller

Intended Use:

—

Supports All Standard DDR SDRAM Memory Types

High-Speed Networking

Embedded Computing

Digital Video

Features:

reset

—

DDR SDRAM dynamic burst length support for burst lengths of

ddr_clk

clkx2

2, 4, or 8 per access

sys_clk

—

Supports DRAM data path widths of 16, 32, 64, and 72 bits

Supports multiple bank interleaving with read and write

commands, and all read and write commands are issued at the

earliest possible time with maximum efficiency

CAS latency 2.0 support

clk_module

fpga_clk

ddr_clk_fb

ddr_addr

ddr_dm

ddr_bank

ddr_ras

ddr_cas

ddr_we

ddr_dqs

ddr_cs

smp_clk

smp_delay

fpga_clk

DDR

sys_cmd

sys_cmd_ack

read_en

Control and Status

fpga_clk

—

SDRAM

controller

Support for the following commands: NOP, LOAD_MODE,

READ, READ w/ AUTO_PRECHARGE, WRITE, WRITE w/

AUTO_PRECHARGE, and AUTO_REFRESH

Data mask support for write operations

ctlr_ready

ddr_interface

ddr_cke

ddr_dq

sys_data_o

sys_data_valid

sys_data_i

sys_data_m

sys_addr

—

Support for 4 internal banks

Controller provides automatic management of all four SDRAM

memory banks simultaneously

Targeted Devices:

—

Axcelerator Family

—

ProASIC 3 Family

Core Deliverables:

—

Netlist Version

Block Diagram

> Netlist compatible with the Actel Designer place and route tool

—

RTL Version

> VHDL Source Code

> Test Bench

All

This core conforms to the appropriate standard(s). In general, standards do not

define the internal user interface, only the external interfaces and protocols. Therefore,

Avnet Memec has created a simple FIFO interface to this core for easy user

connectivity. Please consult the appropriate standards document for all external

signaling. The Double Data Rate (DDR) Synchronous Dynamic Random Access

Memory (SDRAM) controller pro-vides the user with a simplified interface to industry

—

> User Guide

Synthesis and Simulation Support:

standard memory devices. The controller has been targeted to the Actel Axcelerator

—

Synthesis: Synplicity

and ProASIC 3 families of platform FPGAs and can be reconfigured to provide a

Simulation: ModelSim

solution customized to the user’s needs based on system and memory-specific require-

ments. The DDR SDRAM controller offers full support for SDRAM bank and row

management, supports four bank interleaving between commands, and executes all

commands with maximum efficiency. The extensive feature list makes this an extremely

flexible and efficient core to use.

Other tools supported upon request

Veriﬁcation:

—

Test Bench

—

Test Vectors

12 3 4 5

中文翻译

下载PDF

与MC-ACT-SDRAMDDR-NET相关器件

型号	品牌	获取价格	描述	数据表
MC-ACT-SDRAMDDR-VHDL	ACTEL	获取价格	Double Data Rate SDRAM Controller
MC-ACT-UARTF	ACTEL	获取价格	FastUART
MC-ACT-UARTF-NET	ACTEL	获取价格	FastUART
MC-ACT-UARTF-VHD	ACTEL	获取价格	FastUART
MC-ACT-UARTM-NET	ACTEL	获取价格	Multi-Channel UART Controller
MC-ACT-UARTM-VHDL	ACTEL	获取价格	Multi-Channel UART Controller
MC-ACT-UL2LINK-NET	ACTEL	获取价格	Function compatible with ATM Forum af-phy-0017.000 & af-phy-0039.000
MC-ACT-UL2LINK-VHDL	ACTEL	获取价格	Function compatible with ATM Forum af-phy-0017.000 & af-phy-0039.000
MC-ACT-UL2PHY	ACTEL	获取价格	ATM cell processors ATM switch fabrics
MC-ACT-UL3LINK-NET	ACTEL	获取价格	Function compatible with ATM Forum Asynchronous/synchronous FIFO using RAM

与MC-ACT-SDRAMDDR-NET相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

MC-ACT-SDRAMDDR-NET

MC-ACT-SDRAMDDR-NET 技术参数

MC-ACT-SDRAMDDR-NET 数据手册

与MC-ACT-SDRAMDDR-NET相关器件

与MC-ACT-SDRAMDDR-NET相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MC-ACT-SDRAMDDR-NET

MC-ACT-SDRAMDDR-NET 技术参数

MC-ACT-SDRAMDDR-NET 数据手册

与MC-ACT-SDRAMDDR-NET相关器件

与MC-ACT-SDRAMDDR-NET相关文章

您还可以找

您在本页遇到什么问题？