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MC-ACT-UL2LINK-NET

更新时间： 2024-02-16 10:32:44

品牌	Logo	应用领域
ACTEL		异步传输模式 ATM
页数	文件大小	规格书
7页	291K
描述
Function compatible with ATM Forum af-phy-0017.000 & af-phy-0039.000

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技术参数
数据手册

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MC-ACT-UL2LINK-NET 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.82
JESD-30 代码：	R-XXMA-X	封装主体材料：	UNSPECIFIED
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
表面贴装：	NO	端子形式：	UNSPECIFIED
端子位置：	UNSPECIFIED	Base Number Matches：	1

MC-ACT-UL2LINK-NET 数据手册

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AvnetCore: Datasheet

Version 1.0, July 2006

UTOPIA Level 2 Link

Intended Use:

—

ATM Cell Processors

—

ATM Switch Fabrics

Features:

—

Function compatible with ATM Forum af-phy-0017.000 &

af-phy-0039.000

wr_data

wr_enb

wr_clk

egr_data

egr_addr

egr_soc

egr_enb_n

egr_clav

egr_prty

egr_clk

—

Asynchronous/synchronous FIFO using RAM

Up to 31 PHYs supported

rd_data

rd_enb

decrement

empty

a_full

increment

TX FIFO

Master

8/16 bit interfaces supported

52/54 byte cells supported

flag

Simple system side FIFO interface

ing_perr

rd_data

rd_enb

rd_clk

ing_data

ing_addr

ing_soc

Targeted Devices:

wr_data

wr_enb

soc

tex

RX FIFO

flag

—

Axcelerator Family

ing_enb_n

ing_clav

ing_prty

ing_clk

decrement

Master

increment

a_full

Core Deliverables:

—

Netlist Version

> Netlist compatible with the Actel Designer place and route tool

> Compiled RTL simulation model, compliant with the Actel

Libero environment

—

RTL Version

> VHDL Source Code

All

Block Diagram

> User Guide

> Test Bench

Synthesis and Simulation Support:

UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 2 defines the

interface between the ATM or LINK layer and a Physical Layer (PHY) device. The

UTOPIA level 2 standard defines a full duplex interface with a Master/Slave format. The

Slave or LINK layer device responds to the requests from the PHY or Master device.

The Master performs PHY arbitration and initiates data transfers to and from the Slave.

The ATM forum has defined the UTOPIA Level 2 as either 8 or 16 bits in width, at up to

50MHz, supporting an OC12 channel at 622Mbps.

—

Synthesis: Synplicity

Simulation: ModelSim

Other tools supported upon request

Verification:

—

Test Bench

—

Test Vectors

12 3 4 5 6 7

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