Datasheet > MAX3676_09

MAX3676_09

更新时间： 2022-12-29 02:11:15

品牌	Logo	应用领域
美信 - MAXIM		放大器时钟
页数	文件大小	规格书
15页	265K
描述
622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier

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MAX3676_09 数据手册

622Mbps, 3.3V Clock-Recovery and

Data-Retiming IC with Limiting Amplifier

MAX376

The comparator is configured with an active-high LOP

output. An on-chip, 6kΩ pull-up resistor is provided to

reduce the external part count.

Setting the Loop Filter

The MAX3676 is designed for both regenerator and

receiver applications. Its fully integrated PLL is a classic

second-order feedback system, with a loop bandwidth

C = 0.22μF

(f ) fixed at 250kHz. The external capacitor, C , can be

adjusted to set the loop damping. Figures 2 and 3 show

f = 8.04kHz

the open-loop and closed-loop transfer functions. The

C = 2.2μF

PLL zero frequency, f , is a function of external capaci-

tor C , and can be approximated according to:

f = 804Hz

f (Hz)

2π(90) C

100

10k 100k 1M 10M

For an overdamped system (f /f ) <0.25, the jitter peak-

Z L

ing (M ) of a second-order system can be approximat-

ed by:

Figure 2. Open-Loop Transfer Function

⎛

⎝

⎞

= 20log 1+

⎜

⎟

⎠

For example, using C = 0.22μF results in a jitter peak-

ing of 0.27dB. Reducing C below 0.22μF may result in

PLL instability. The recommended value for C is 2.2μF

to guarantee a maximum jitter peaking of less than

0.1dB.

H(J2πf) (dB)

C = 0.22μF

The MAX3676 is optimally designed to acquire lock and

to provide a bit-error rate (BER) of less than 10^-10for

long strings of consecutive zeros and ones. Measured

results show that the MAX3676 can tolerate 1200 con-

-3

C = 2.2μF

secutive ones or zeros. Decreasing C reduces the

number of tolerated consecutive identical zeros and

ones. C must be a low-TC, high-quality capacitor of

type X7R or better.

Lock Detect

The MAX3676’s LOL monitor indicates when the PLL is

locked. Under normal operation, the loop is locked and

the LOL output signal is high. When the MAX3676 loses

lock, a fast negative-edge transition occurs on LOL.

f (kHz)

100

10k 100k 1M 10M

The output level remains at a low level (held by C

until the loop reacquires lock (Figure 4).

)

LOL

Figure 3. Closed-Loop Transfer Function

_______________________________________________________________________________________

1...6 7 8910 11 12...15

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与MAX3676_09相关器件

型号	品牌	获取价格	描述	数据表
MAX3676E/D	MAXIM	获取价格	622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
MAX3676EHJ	MAXIM	获取价格	622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
MAX3676EHJ+	MAXIM	获取价格	622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
MAX3676EHJ+T	MAXIM	获取价格	ATM/SONET/SDH Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, TQFP
MAX3676EHJ-T	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, TQFP-32
MAX3676EVKIT	MAXIM	获取价格	Evaluation Kit for the MAX3675/MAX3676
MAX3678	MAXIM	获取价格	Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching
MAX3678EVKIT	MAXIM	获取价格	Evaluation Kit for the MAX3678
MAX3679	MAXIM	获取价格	+3.3V, Low-Jitter Crystal to LVPECL Clock Generator
MAX3679A	MAXIM	获取价格	+3.3V, Low-Jitter Crystal to LVPECL Clock Generator

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