Datasheet > MAX3676_09

MAX3676_09

更新时间： 2022-12-29 02:11:15

品牌	Logo	应用领域
美信 - MAXIM		放大器时钟
页数	文件大小	规格书
15页	265K
描述
622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier

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MAX3676_09 数据手册

622Mbps, 3.3V Clock-Recovery and

Data-Retiming IC with Limiting Amplifier

MAX376

LOL

PHADJ+ PHADJ- FIL+ FIL-

SDO+

SDO-

6kΩ

PECL

DDI+

DDI-

SCLKO+

SCLKO-

PHASE/FREQ

DETECTOR

PECL

FILTER

VCO

INSEL

622.08MHz

ADI-

ADI+

1.23V

LIMITER

42dB

BIAS

6kΩ

POWER

DETECT

OFFSET

CORRECTION

MAX3676

OLC+ OLC-

CFILT

RSSI INV

VTH

LOP

Figure 1. Functional Diagram

viding excellent sensitivity for small-amplitude data

streams.

_______________Detailed Description

The block diagram in Figure 1 shows the MAX3676’s

architecture. It consists of a limiting-amplifier input

stage followed by a fully integrated clock/data-recovery

(CDR) block implemented with a PLL. The input stage

is selectable between a limiting amplifier or a simple

PECL input buffer. The limiting amplifier provides an

LOP monitor and an RSSI output. The PLL consists of a

phase/frequency detector (PFD), a loop filter amplifier,

and a voltage-controlled oscillator (VCO).

In addition to driving the CDR, the limiting amplifier pro-

vides both an RSSI output and an LOP monitor that

allow the user to program the threshold voltage. The

RSSI circuitry provides an output voltage that is linearly

proportional to the input power (in decibels) detected

between the ADI+ and ADI- input pins and is sensitive

enough to reliably detect signals as small as 2mV

(see the Typical Operating Characteristics).

P-P

Input DC offset reduces the accuracy of the power

detector; therefore, an integrated feedback loop is

included that automatically nulls the input offset of the

gain stage. The addition of this offset-correction loop

requires that the input signal be AC-coupled when

using the ADI+ and ADI- inputs.

Limiting Amplifier

The MAX3676’s on-chip limiting amplifier accepts an

input signal level from 3.0mV

to 1.2V . The amplifi-

P-P

er consists of a cascade of gain stages that include full-

wave logarithmic detectors. The combined small-signal

gain is approximately 42dB, and the -3dB bandwidth is

Finally, for applications that do not require the limiting

amplifier, selecting the digital inputs conserves power

by turning off the postamplifier block.

650MHz. Input-referred noise is typically 80μV

, pro-

RMS

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