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MAX3624UTJ+T

更新时间: 2024-09-16 14:34:27
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
13页 409K
描述
Clock Generator, CMOS

MAX3624UTJ+T 技术参数

是否无铅:不含铅生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
JESD-609代码:e3湿度敏感等级:1
峰值回流温度(摄氏度):225技术:CMOS
端子面层:MATTE TIN处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

MAX3624UTJ+T 数据手册

 浏览型号MAX3624UTJ+T的Datasheet PDF文件第2页浏览型号MAX3624UTJ+T的Datasheet PDF文件第3页浏览型号MAX3624UTJ+T的Datasheet PDF文件第4页浏览型号MAX3624UTJ+T的Datasheet PDF文件第5页浏览型号MAX3624UTJ+T的Datasheet PDF文件第6页浏览型号MAX3624UTJ+T的Datasheet PDF文件第7页 
19-0977; Rev 1; 11/07  
Low-Jitter, Precision Clock Generator  
with Four Outputs  
MAX3624  
General Description  
Features  
Crystal Oscillator Interface: 19.375MHz to 27MHz  
CMOS Input: 19MHz to 40.5MHz  
The MAX3624 is a low-jitter precision clock generator  
optimized for networking applications. The device inte-  
grates a crystal oscillator and a phase-locked loop  
(PLL) clock multiplier to generate high-frequency clock  
outputs for Ethernet, Fibre Channel, SONET/SDH, and  
other networking applications.  
Output Frequencies  
Ethernet: 62.5MHz, 125MHz, 156.25MHz,  
312.5MHz  
Fibre Channel: 106.25MHz, 159.375MHz,  
212.5MHz, 318.5MHz  
Maxim’s proprietary PLL design features ultra-low jitter  
(0.36ps  
) and excellent power-supply noise rejec-  
RMS  
SONET/SDH: 77.76MHz, 155.52MHz, 311.04MHz  
tion, minimizing design risk for network equipment.  
Low Jitter  
The MAX3624 has three LVPECL outputs and one  
LVCMOS output. Selectable output dividers and a  
selectable feedback divider allow a range of output  
frequencies.  
0.14ps  
0.36ps  
(1.875MHz to 20MHz)  
(12kHz to 20MHz)  
RMS  
RMS  
Excellent Power-Supply Noise Rejection  
No External Loop Filter Capacitor Required  
Applications  
Ethernet Networking Equipment  
Fibre Channel Storage Area Network  
SONET/SDH Network  
Ordering Information  
PKG  
PART  
TEMP RANGE PIN-PACKAGE  
CODE  
MAX3624UTJ+ 0°C to +85°C 32 TQFN-EP*  
T3255-3  
Pin Configuration and Typical Application Circuit appear at  
end of data sheet.  
+Denotes a lead-free package.  
*EP = Exposed pad.  
Block Diagram  
IN_SEL  
MR  
BYPASS  
SELA[1:0]  
QAC_OE  
QA_C  
LVCMOS  
BUFFER  
SELA[1:0]  
SELB[1:0]  
FB_SEL[1:0]  
BYPASS  
RESET LOGIC/POR  
RESET  
DIVIDER  
NA  
QA_OE  
QA  
LVPECL  
BUFFER  
RESET  
QA  
0
1
LVCMOS  
REF_IN  
0
1
620MHz TO 648MHz  
VCO  
QB1_OE  
QB1  
PFD  
FILTER  
RESET  
27pF  
X_IN  
LVPECL  
BUFFER  
RESET  
QB1  
CRYSTAL  
OSCILLATOR  
DIVIDER  
M
DIVIDER  
NB  
X_OUT  
33pF  
QB0_OE  
QB0  
DIVIDERS:  
LVPECL  
BUFFER  
M = 16, 24, 25, 32  
NA = 1, 2, 3, 4, 5, 6, 8, 10, 12  
NB = 1, 2, 3, 4, 5, 6, 8, 10, 12  
QB0  
MAX3624  
FB_SEL[1:0]  
SELB[1:0]  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  

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