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MAX3625ACUG+ PDF预览

MAX3625ACUG+

更新时间: 2024-11-28 05:49:03
品牌 Logo 应用领域
美信 - MAXIM 晶体时钟发生器外围集成电路光电二极管信息通信管理
页数 文件大小 规格书
10页 302K
描述
Low-Jitter, Precision Clock Generator with Three Outputs

MAX3625ACUG+ 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:TSSOP,
针数:24Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.52JESD-30 代码:R-PDSO-G24
长度:7.8 mm端子数量:24
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:318.75 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:27 MHz认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

MAX3625ACUG+ 数据手册

 浏览型号MAX3625ACUG+的Datasheet PDF文件第2页浏览型号MAX3625ACUG+的Datasheet PDF文件第3页浏览型号MAX3625ACUG+的Datasheet PDF文件第4页浏览型号MAX3625ACUG+的Datasheet PDF文件第5页浏览型号MAX3625ACUG+的Datasheet PDF文件第6页浏览型号MAX3625ACUG+的Datasheet PDF文件第7页 
19-4626; Rev 0; 5/09  
Low-Jitter, Precision Clock  
Generator with Three Outputs  
MX3625A  
General Description  
Features  
The MAX3625A is a low-jitter, precision clock generator  
optimized for networking applications. The device inte-  
grates a crystal oscillator and a phase-locked loop  
(PLL) clock multiplier to generate high-frequency clock  
outputs for Ethernet, 10G Fibre Channel, and other net-  
working applications.  
Crystal Oscillator Interface: 24.8MHz to 27MHz  
CMOS Input: Up to 320MHz  
Output Frequencies  
Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz  
10G Fibre Channel: 159.375MHz, 318.75MHz  
Low Jitter  
Maxim’s proprietary PLL design features ultra-low jitter  
and excellent power-supply noise rejection, minimizing  
design risk for network equipment.  
0.14ps  
0.36ps  
(1.875MHz to 20MHz)  
(12kHz to 20MHz)  
RMS  
RMS  
Excellent Power-Supply Noise Rejection  
No External Loop Filter Capacitor Required  
The MAX3625A has three LVPECL outputs. Selectable  
output dividers and a selectable feedback divider allow  
a range of output frequencies.  
Applications  
Ordering Information  
Ethernet Networking Equipment  
PART  
TEMP RANGE  
PIN-PACKAGE  
Fibre Channel Storage Area Network  
MAX3625ACUG+  
0°C to +70°C  
24 TSSOP  
+Denotes a lead(Pb)-free/RoHS-compliant package.  
Pin Configuration and Typical Application Circuit appear at  
end of data sheet.  
Block Diagram  
IN_SEL  
MR  
BYPASS  
SELA[1:0]  
QA_OE  
QA  
SELA[1:0]  
SELB[1:0]  
FB_SEL  
RESET LOGIC/POR  
RESET  
DIVIDER  
NA  
LVPECL  
BUFFER  
BYPASS  
QA  
RESET  
0
1
LVCMOS  
REF_IN  
0
1
620MHz TO 648MHz  
VCO  
PFD  
FILTER  
RESET  
27pF  
X_IN  
QB1  
QB1  
LVPECL  
BUFFER  
RESET  
CRYSTAL  
OSCILLATOR  
DIVIDER  
M
DIVIDER  
NB  
X_OUT  
33pF  
QB_OE  
QB0  
DIVIDERS:  
LVPECL  
BUFFER  
M = 24, 25  
NA = 10, 2, 4, 5  
NB = 10, 2, 4, 5  
QB0  
MAX3625A  
FB_SEL  
SELB[1:0]  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  

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