Datasheet > MACH435Q-25JC

MACH435Q-25JC

更新时间： 2024-10-28 22:13:31

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑
页数	文件大小	规格书
30页	252K
描述
High-Density EE CMOS Programmable Logic

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技术参数
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MACH435Q-25JC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ, LDCC84,1.2SQ	针数：	84
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.85
其他特性：	NO	最大时钟频率：	21.3 MHz
系统内可编程：	NO	JESD-30 代码：	S-PQCC-J84
JESD-609代码：	e0	JTAG BST：	NO
长度：	29.2862 mm	湿度敏感等级：	3
专用输入次数：	2	I/O 线路数量：	64
宏单元数：	128	端子数量：	84
最高工作温度：	70 °C	最低工作温度：
组织：	2 DEDICATED INPUTS, 64 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC84,1.2SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	25 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	29.2862 mm
Base Number Matches：	1

MACH435Q-25JC 数据手册

FINAL

COM’L: -12/15/20, Q-20/25

Lattice Semiconductor

MACH435-12/15/20, Q-20/25

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

■ 84 Pins in PLCC

■ Flexible clocking

■ 128 Macrocells

— Four global clock pins with selectable edges

— Asynchronous mode available for each

macrocell

■ 12 ns tPD

■ 83.3 MHz fCNT

■ 8 “PAL33V16” blocks

■ 70 Inputs with pull-up resistors

■ 64 Outputs

■ Input and output switch matrices for high

routability

■ 192 Flip-flops

■ Fixed, predictable, deterministic delays

— 128 Macrocell flip-flops

— 64 Input flip-flops

■ Pin compatible with MACH130, MACH131,

MACH230, and MACH231

■ Up to 20 product terms per function, with XOR

GENERAL DESCRIPTION

TheMACH435isamemberofourhigh-performance

EE CMOS MACH 4 family. This device has approxi-

mately twelve times the macrocell capability of the

popular PAL22V10, with significant density and func-

tional features that the PAL22V10 does not provide.

together on the same device. The two types of design

can be mixed in any proportion, since the selection on

each macrocell affects only that macrocell.

Up to 20 product terms per function can be assigned. It

is possible to allocate some product terms away from a

macrocell without losing the use of that macrocell for

logic generation.

The MACH435 consists of eight PAL blocks intercon-

nected by a programmable central switch matrix. The

central switch matrix connects the PAL blocks to each

other and to all input pins, providing a high degree of

connectivity between the fully-connected PAL blocks.

This allows designs to be placed and routed efficiently.

Routability is further enhanced by an input switch matrix

and an output switch matrix. The input switch matrix

provides input signals with alternative paths into the

central switch matrix; the output switch matrix provides

flexibility in assigning macrocells to I/O pins.

The MACH435 macrocell provides either registered or

combinatorial outputs with programmable polarity. If a

registered configuration is chosen, the register can be

configured as D-type, T-type, J-K, or S-R to help reduce

the number of product terms used. The flip-flop can also

be configured as a latch. The register type decision can

be made by the designer or by the software.

All macrocells can be connected to an I/O cell through

the output switch matrix. The output switch matrix

makes it possible to make significant design changes

while minimizing the risk of pinout changes.

The MACH435 has macrocells that can be configured

assynchronousorasynchronous.Thisallowsdesigners

to implement both synchronous and asynchronous logic

Publication# 17469 Rev. E Amendment/0

Issue Date: May 1995

12 3 4 5 6 7...30

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与MACH435Q-25JC相关器件

型号	品牌	获取价格	描述	数据表
MACH445-12	LATTICE	获取价格	High-Density EE CMOS Programmable Logic
MACH445-12YC	LATTICE	获取价格	High-Density EE CMOS Programmable Logic
MACH445-15YC	LATTICE	获取价格	High-Density EE CMOS Programmable Logic
MACH445-20YC	LATTICE	获取价格	High-Density EE CMOS Programmable Logic
MACH465-12YC	ROCHESTER	获取价格	EE PLD, 16ns, PQFP208, PLASTIC, QFP-208
MACH4-96	LATTICE	获取价格	High-Performance EE CMOS Programmable Logic
MACH4-96/96-15YC	LATTICE	获取价格	High-Performance EE CMOS Programmable Logic
MACH5	LATTICE	获取价格	Fifth Generation MACH Architecture
MACHLV210-12	LATTICE	获取价格	High Density EE CMOS Programmable Logic
MACHLV210-12JC	LATTICE	获取价格	High Density EE CMOS Programmable Logic

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