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MACH445-20YC

更新时间： 2024-10-28 22:33:07

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
28页	212K
描述
High-Density EE CMOS Programmable Logic

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MACH445-20YC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	QFP, QFP100,.7X.9
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.85
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	30.3 MHz	系统内可编程：	YES
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
JTAG BST：	YES	湿度敏感等级：	3
专用输入次数：	2	I/O 线路数量：	64
宏单元数：	128	端子数量：	100
最高工作温度：	70 °C	最低工作温度：
组织：	2 DEDICATED INPUTS, 64 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.7X.9	封装形状：	RECTANGULAR
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	225
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	20 ns	认证状态：	Not Qualified
子类别：	Programmable Logic Devices	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

MACH445-20YC 数据手册

FINAL

COM’L: -12/15/20

Lattice Semiconductor

MACH445-12/15/20

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

■ 100-pin version of the MACH435 in PQFP

■ 5 V, in-circuit programmable

■ JTAG, IEEE 1149.1 JTAG testing capability

■ 128 macrocells

■ Up to 20 product terms per function, with XOR

■ Flexible clocking

— Four global clock pins with selectable edges

— Asynchronous mode available for each

macrocell

■ 12 ns t_PD

■ 8 “PAL33V16” blocks

■ 83 MHz f_CNT

■ Input and output switch matrices for high

■ 70 inputs with pull-up resistors

■ 64 outputs

routability

■ Fixed, predictable, deterministic delays

■ JEDEC-file compatible with MACH435

■ Zero-hold-time input register option

■ 192 flip-flops

— 128 macrocell flip-flops

— 64 input flip-flops

GENERAL DESCRIPTION

TheMACH445isamemberofthehigh-performance

EE CMOS MACH 4 family. This device has approxi-

mately twelve times the macrocell capability of the

popular PAL22V10, with significant density and func-

tional features that the PAL22V10 does not provide. It is

architecturally identical to the MACH435, with the

addition of JTAG and 5-V programming features.

asynchronous logic together on the same device. The

two types of design can be mixed in any proportion,

since the selection on each macrocell affects only that

macrocell.

Up to 20 product terms per function can be assigned. It

is possible to allocate some product terms away from a

macrocell without losing the use of that macrocell for

logic generation.

The MACH445 consists of eight PAL blocks intercon-

nected by a programmable central switch matrix. The

central switch matrix connects the PAL blocks to each

other and to all input pins, providing a high degree of

connectivity between the fully-connected PAL blocks.

This allows designs to be placed and routed efficiently.

Routability is further enhanced by an input switch matrix

and an output switch matrix. The input switch matrix

provides input signals with alternative paths into the

central switch matrix; the output switch matrix provides

flexibility in assigning macrocells to I/O pins.

The MACH445 macrocell provides either registered or

combinatorial outputs with programmable polarity. If a

registered configuration is chosen, the register can be

configured as D-type, T-type, J-K, or S-R to help reduce

the number of product terms used. The flip-flop can also

be configured as a latch. The register type decision can

be made by the designer or by the software.

All macrocells can be connected to an I/O cell through

the output switch matrix. The output switch matrix

makes it possible to make significant design changes

while minimizing the risk of pinout changes.

The MACH445 has macrocells that can be configured

as synchronous or asynchronous. This allows

designers to implement both synchronous and

Publication# 17468 Rev. E Amendment/0

Issue Date: May 1995

12 3 4 5 6 7...28

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与MACH445-20YC相关器件

型号	品牌	获取价格	描述	数据表
MACH465-12YC	ROCHESTER	获取价格	EE PLD, 16ns, PQFP208, PLASTIC, QFP-208
MACH4-96	LATTICE	获取价格	High-Performance EE CMOS Programmable Logic
MACH4-96/96-15YC	LATTICE	获取价格	High-Performance EE CMOS Programmable Logic
MACH5	LATTICE	获取价格	Fifth Generation MACH Architecture
MACHLV210-12	LATTICE	获取价格	High Density EE CMOS Programmable Logic
MACHLV210-12JC	LATTICE	获取价格	High Density EE CMOS Programmable Logic
MACHLV210-15JC	LATTICE	获取价格	High Density EE CMOS Programmable Logic
MACHLV210-20JC	LATTICE	获取价格	High Density EE CMOS Programmable Logic
MACHLV210-24JI	LATTICE	获取价格	EE PLD, 24ns, 64-Cell, CMOS, PQCC44, PLASTIC, LCC-44
MACHXO	LATTICE	获取价格	MachXO Family Data Sheet

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