Datasheet > MACH4-96

MACH4-96

更新时间： 2024-10-28 22:28:31

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑
页数	文件大小	规格书
33页	290K
描述
High-Performance EE CMOS Programmable Logic

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数据手册

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MACH4-96 数据手册

MACH 4 FAMILY

FINAL

COM’L: -15

IND: -18

Lattice Semiconductor

MACH4-96/96-15

High-Performance EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

◆ 144 Pins in PQFP

◆ 96 Macrocells

◆ 15 ns t Commercial, 18 ns t Industrial

◆ 47.6 MHz f

CNT

◆ 102 Inputs w ith pull-up resistors

◆ 96 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

◆ 96 Flip-ﬂops

◆ Up to 20 product terms per macrocell, w ith XOR

◆ Flexible clocking

— Four global clock pins with selectable edges

— Asynchronous mode available for each macrocell

◆ 3 MACH111SP-size blocks

◆ SpeedLocking™ for guaranteed ﬁxed timing

◆ JTAG, 5-V, in-system programmable

◆ JTAG (IEEE 1149.1) boundary scan testing capability

◆ Input and output sw itch matrices for high routability

PLEASE NOTE: The MACH4-96/96 (M4-96/96) reﬂects a new nomenclature for the MACH 4 Family.

This device is currently dual-marked with the MACH355 ordering part number. The dual-mark

scheme will facilitate design and manufacturing ﬂows until we have completely phased in the new

M4-96/96 nomenclature. Please use the MACH355 data sheet (PID# 17467) as a reference.

GENERAL DESCRIPTION

The MACH4-96/96 (M4-96/96) is a member of Vantis’ high-performance EE CMOS MACH 4 family.

This device has approximately three times the macrocell capability of the popular MACH111SP,

with signiﬁcant additional density and functional features.

The M4-96/96 consists of six PAL^®blocks interconnected by a programmable central switch matrix.

The central switch matrix connects the PAL blocks to each other and to all input pins, providing a

high degree of connectivity between the PAL blocks. This allows designs to be placed and routed

efﬁciently. Routability is further enhanced by an input switch matrix and an output switch matrix.

The input switch matrix provides input signals with alternative paths into the central switch matrix;

the output switch matrix provides ﬂexibility in assigning macrocells to I/O pins.

Publication# 21 535

Amendment/+1

Rev: A

Issue Date: November 1 997

12 3 4 5 6 7...33

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