Datasheet > MACHLV210-12

MACHLV210-12

更新时间： 2024-10-28 22:28:31

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑
页数	文件大小	规格书
29页	219K
描述
High Density EE CMOS Programmable Logic

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中文翻译

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MACHLV210-12 数据手册

FINAL

COM’L: -12/15/20

IND: -18/24

Lattice Semiconductor

MACHLV210-12/15/20

High Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

■ Low-voltage operation, 3.3-V JEDEC

■ 83.3 MHz fCNT

■ 38 Bus-Friendly Inputs

compatible

— VCC = +3.0 V to +3.6 V

■ < 5 mA standby current

■ 32 Outputs

■ 64 Flip-flops; 2 clock choices

■ 4 “PAL22V16” blocks with buried macrocells

■ Patented design allows minimal standby

current without speed degradation

■ Pin-, function-, and JEDEC-compatible with

■ Exclusively designed for 3.3-V applications

■ 44 Pins

MACH210

■ Pin-compatible with MACH110, MACH111,

■ 64 Macrocells

MACH210, MACH211, and MACH215

■ 12 ns tPDCommercial

18 ns tPDIndustrial

GENERAL DESCRIPTION

The MACHLV210 is a member of the high-

performance EE CMOS MACH 2 device family. This

device has approximately six times the logic macrocell

capability of the popular PAL22V10 at an equal speed

with a lower cost per macrocell. It is architecturally

identical to the MACH210, with the addition of I/O

pull-up/pull-down resistors and low-voltage, low-power

operation.

matrix connects the PAL blocks to each other and to all

input pins, providing a high degree of connectivity

between the fully-connected PAL blocks. This allows

designs to be placed and routed efficiently.

The MACHLV210 has two kinds of macrocell: output

and buried. The MACHLV210 output macrocell pro-

vides registered, latched, or combinatorial outputs with

programmable polarity. If a registered configuration is

chosen, the register can be configured as D-type or

T-type to help reduce the number of product terms. The

the software. All output macrocells can be connected to

an I/O cell. If a buried macrocell is desired, the internal

feedback path from the macrocell can be used, which

frees up the I/O pin for use as an input.

The MACHLV210 provides 3.3-V operation with low-

power CMOS technology. The patented design

allows for minimal standby current without speed

degradation by limiting the leakage current when

signals are not switching. At less than 5 mA maximum

standby current, the MACHLV210 is ideal for low-power

applications.

The MACHLV210 consists of four PAL blocks intercon-

nected by a programmable switch matrix. The four PAL

blocks are essentially “PAL22V16” structures complete

with product-term arrays and programmable macro-

cells, including additional buried macrocells. The switch

The MACHLV210 has dedicated buried macrocells

which, in addition to the capabilities of the output

macrocell, also provide input registers or latches for

use in synchronizing signals and reducing setup time

requirements.

Publication# 17908 Rev. D Amendment/0

Issue Date: May 1995

12 3 4 5 6 7...29

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与MACHLV210-12相关器件

型号	品牌	获取价格	描述	数据表
MACHLV210-12JC	LATTICE	获取价格	High Density EE CMOS Programmable Logic
MACHLV210-15JC	LATTICE	获取价格	High Density EE CMOS Programmable Logic
MACHLV210-20JC	LATTICE	获取价格	High Density EE CMOS Programmable Logic
MACHLV210-24JI	LATTICE	获取价格	EE PLD, 24ns, 64-Cell, CMOS, PQCC44, PLASTIC, LCC-44
MACHXO	LATTICE	获取价格	MachXO Family Data Sheet
MACP-007486-CH0010	TE	获取价格	17dB Coupler 5-1000MHz
MACP-007486-CH0010	MACOM	获取价格	Coupler, 17dB 5 - 1000 MHz
MACP-007486-CH0010_15	TE	获取价格	17dB Coupler
MACP-007486-CH0010-V2	TE	获取价格	17dB Coupler
MACP-007486-CH00TB	TE	获取价格	17dB Coupler 5-1000MHz

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