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MACH110-20 PDF预览

MACH110-20

更新时间: 2024-10-27 22:37:19
品牌 Logo 应用领域
超微 - AMD 可编程逻辑
页数 文件大小 规格书
28页 180K
描述
High-Density EE CMOS Programmable Logic

MACH110-20 数据手册

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FINAL  
COM’L: -12/15/20  
IND: -14/18/24  
Advanced  
Micro  
MACH110-12/15/20  
High-Density EE CMOS Programmable Logic  
Devices  
DISTINCTIVE CHARACTERISTICS  
44 Pins  
32 Outputs  
32 Macrocells  
32 Flip-flops; 2 clock choices  
2 “PAL22V16” Blocks  
12 ns tPD Commercial  
14 ns tPD Industrial  
Pin-compatible with MACH111, MACH210,  
MACH211, MACH215  
77 MHz fCNT  
38 Inputs  
GENERAL DESCRIPTION  
TheMACH110isamemberofAMD’shigh-performance  
EE CMOS MACH 1 family. This device has approxi-  
mately three times the logic macrocell capability of the  
popular PAL22V10 without loss of speed.  
The MACH110 macrocell provides either registered or  
combinatorial outputs with programmable polarity. If a  
registered configuration is chosen, the register can be  
configured as D-type or T-type to help reduce the  
number of product terms. The register type decision can  
be made by the designer or by the software. All  
macrocells can be connected to an I/O cell. If a buried  
macrocell is desired, the internal feedback path from the  
macrocell can be used, which frees up the I/O pin for use  
as an input.  
The MACH110 consists of two PAL blocks intercon-  
nected by a programmable switch matrix. The two PAL  
blocks are essentially “PAL22V16” structures complete  
with product-term arrays and programmable macro-  
cells. The switch matrix connects the PAL blocks to  
each other and to all input pins, providing a high degree  
of connectivity between the fully-connected PAL blocks.  
This allows designs to be placed and routed efficiently.  
Publication# 14127 Rev. I  
Issue Date: May 1995  
Amendment/0  

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