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MACH111-12JI PDF预览

MACH111-12JI

更新时间: 2024-10-27 22:37:19
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
48页 1080K
描述
High-Performance EE CMOS Programmable Logic

MACH111-12JI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-44
针数:44Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.68Is Samacsys:N
其他特性:NO最大时钟频率:66.7 MHz
系统内可编程:NOJESD-30 代码:S-PQCC-J44
JESD-609代码:e0JTAG BST:NO
长度:16.5862 mm湿度敏感等级:3
专用输入次数:2I/O 线路数量:64
宏单元数:32端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
组织:2 DEDICATED INPUTS, 64 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
可编程逻辑类型:EE PLD传播延迟:12 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:16.5862 mm
Base Number Matches:1

MACH111-12JI 数据手册

 浏览型号MACH111-12JI的Datasheet PDF文件第2页浏览型号MACH111-12JI的Datasheet PDF文件第3页浏览型号MACH111-12JI的Datasheet PDF文件第4页浏览型号MACH111-12JI的Datasheet PDF文件第5页浏览型号MACH111-12JI的Datasheet PDF文件第6页浏览型号MACH111-12JI的Datasheet PDF文件第7页 
MACH 1 and 2 CPLD Families  
High-Performance EE CMOS Programmable Logic  
FEATURES  
  High-performance electrically-erasable CMOS PLD families  
  32 to 128 macrocells  
  44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages  
  SpeedLocking™ – guaranteed fixed timing up to 16 product terms  
  Commercial 5/5.5/6/7.5/10/12/15-ns t and Industrial 7.5/10/12/14/18-ns t  
PD  
PD  
  Configurable macrocells  
— Programmable polarity  
— Registered or combinatorial outputs  
— Internal and I/O feedback paths  
— D-type or T-type flip-ops  
— Output Enables  
— Choice of clocks for each flip-flop  
— Input registers for MACH 2 family  
  JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available  
  Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns  
  Safe for mixed supply voltage system designs  
  Bus-Friendly™ inputs and I/Os reduce risk of unw anted oscillatory outputs  
  Programmable pow er-dow n mode results in pow er savings of up to 75%  
  Supported by Vantis DesignDirect™ softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for Vantis  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice/Vantis and third-party hardw are programming support  
®
Lattice/VantisPRO™ (formerly known as MACHPRO ) software for in-system programmability  
support on PCs and Automated Test Equipment  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# 1 4051  
Amendment/0  
Rev: K  
Issue Date: November 1 998  

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