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MACH111-15VC PDF预览

MACH111-15VC

更新时间: 2024-10-27 22:37:19
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑输入元件时钟
页数 文件大小 规格书
48页 1080K
描述
High-Performance EE CMOS Programmable Logic

MACH111-15VC 数据手册

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MACH 1 and 2 CPLD Families  
High-Performance EE CMOS Programmable Logic  
FEATURES  
  High-performance electrically-erasable CMOS PLD families  
  32 to 128 macrocells  
  44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages  
  SpeedLocking™ – guaranteed fixed timing up to 16 product terms  
  Commercial 5/5.5/6/7.5/10/12/15-ns t and Industrial 7.5/10/12/14/18-ns t  
PD  
PD  
  Configurable macrocells  
— Programmable polarity  
— Registered or combinatorial outputs  
— Internal and I/O feedback paths  
— D-type or T-type flip-ops  
— Output Enables  
— Choice of clocks for each flip-flop  
— Input registers for MACH 2 family  
  JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available  
  Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns  
  Safe for mixed supply voltage system designs  
  Bus-Friendly™ inputs and I/Os reduce risk of unw anted oscillatory outputs  
  Programmable pow er-dow n mode results in pow er savings of up to 75%  
  Supported by Vantis DesignDirect™ softw are for rapid logic development  
— Supports HDL design methodologies with results optimized for Vantis  
— Flexibility to adapt to user requirements  
— Software partnerships that ensure customer success  
  Lattice/Vantis and third-party hardw are programming support  
®
Lattice/VantisPRO™ (formerly known as MACHPRO ) software for in-system programmability  
support on PCs and Automated Test Equipment  
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,  
and System General  
Publication# 1 4051  
Amendment/0  
Rev: K  
Issue Date: November 1 998  

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