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MACH110-24JI PDF预览

MACH110-24JI

更新时间: 2024-10-28 15:44:59
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
24页 184K
描述
EE PLD, 24ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44

MACH110-24JI 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:PLASTIC, LCC-44针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:N其他特性:NO
最大时钟频率:30 MHz系统内可编程:NO
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
JTAG BST:NO长度:16.5862 mm
湿度敏感等级:3专用输入次数:4
I/O 线路数量:32宏单元数:32
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C组织:4 DEDICATED INPUTS, 32 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:5 V
可编程逻辑类型:EE PLD传播延迟:24 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.5862 mmBase Number Matches:1

MACH110-24JI 数据手册

 浏览型号MACH110-24JI的Datasheet PDF文件第2页浏览型号MACH110-24JI的Datasheet PDF文件第3页浏览型号MACH110-24JI的Datasheet PDF文件第4页浏览型号MACH110-24JI的Datasheet PDF文件第5页浏览型号MACH110-24JI的Datasheet PDF文件第6页浏览型号MACH110-24JI的Datasheet PDF文件第7页 
FINAL  
COM’L: -12/15/20  
IND: -14/18/24  
Lattice Semiconductor  
MACH110-12/15/20  
High-Density EE CMOS Programmable Logic  
DISTINCTIVE CHARACTERISTICS  
44 Pins  
32 Outputs  
32 Flip-flops; 2 clock choices  
32 Macrocells  
2 “PAL22V16” Blocks  
12 ns tPD Commercial  
14 ns tPD Industrial  
Pin-compatible with MACH111, MACH210,  
MACH211, MACH215  
77 MHz fCNT  
38 Inputs  
GENERAL DESCRIPTION  
TheMACH110isamemberofourhigh-performance  
EE CMOS MACH 1 family. This device has approxi-  
mately three times the logic macrocell capability of the  
popular PAL22V10 without loss of speed.  
The MACH110 macrocell provides either registered or  
combinatorial outputs with programmable polarity. If a  
registered configuration is chosen, the register can be  
configured as D-type or T-type to help reduce the  
number of product terms. The register type decision can  
be made by the designer or by the software. All  
macrocells can be connected to an I/O cell. If a buried  
macrocell is desired, the internal feedback path from the  
macrocell can be used, which frees up the I/O pin for use  
as an input.  
The MACH110 consists of two PAL blocks intercon-  
nected by a programmable switch matrix. The two PAL  
blocks are essentially “PAL22V16” structures complete  
with product-term arrays and programmable macro-  
cells. The switch matrix connects the PAL blocks to  
each other and to all input pins, providing a high degree  
of connectivity between the fully-connected PAL blocks.  
This allows designs to be placed and routed efficiently.  
Publication# 14127 Rev. I  
Issue Date: May 1995  
Amendment/0  

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