MC74VHC1GT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT126 is a single gate noninverting 3−state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC1GT126 requires the 3−state control input (OE) to be
set Low to place the output into the high impedance state.
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MARKING
DIAGRAMS
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT126 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
5
5
1
W3 M G
SC−88A / SOT−353 / SC−70
DF SUFFIX
G
CASE 419A
1
5
5
W3 M G
G
1
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
1
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
CASE 483
Features
• High Speed: t = 3.5 ns (Typ) at V = 5 V
W3 = Device Code
PD
CC
M
G
= Date Code*
= Pb−Free Package
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V
IL
IH
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC
OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 62; Equivalent Gates = 16
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
PIN ASSIGNMENT
1
2
3
4
5
OE
IN A
GND
OUT Y
• These Devices are Pb−Free and are RoHS Compliant
V
CC
OE
IN A
GND
5
4
V
CC
1
2
3
FUNCTION TABLE
OE Input
A Input
Y Output
L
H
X
H
H
L
L
H
Z
OUT Y
Figure 1. Pinout (Top View)
OE
IN A
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
May, 2012 − Rev. 15
MC74VHC1GT126/D