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M74VHCT126ADTR2G PDF预览

M74VHCT126ADTR2G

更新时间： 2024-11-22 11:12:59
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 242K
描述
Quad Bus Buffer, 3-State, TTL Level

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M74VHCT126ADTR2G 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：SOIC包装说明：SOP, SOP14,.25
针数：14Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.49控制类型：ENABLE HIGH
系列：AHCT/VHCT/VTJESD-30 代码：R-PDSO-G14
JESD-609代码：e4长度：8.65 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.008 A湿度敏感等级：1
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：8.5 ns传播延迟（tpd）：11.5 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

M74VHCT126ADTR2G 数据手册

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MC74VHCT126A  
Quad Bus Buffer  
with 3−State Control Inputs  
The MC74VHCT126A is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves  
noninverting high speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining CMOS low power dissipation.  
The MC74VHCT126A requires the 3−state control input (OE) to be  
set Low to place the output into high impedance.  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3 V to 5.0 V, because it  
has full 5.0 V CMOS level output swings.  
www.onsemi.com  
MARKING  
DIAGRAMS  
14  
SOIC−14  
D SUFFIX  
CASE 751A  
VHCT126AG  
AWLYWW  
The VHCT126A input structures provide protection when voltages  
between 0 V and 5.5 V are applied, regardless of the supply voltage.  
1
1
The output structures also provide protection when V = 0 V. These  
CC  
input and output structures help prevent device destruction caused by  
supply voltage − input/output voltage mismatch, battery backup, hot  
insertion, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
14  
VHCT  
126A  
ALYWG  
G
TSSOP−14  
DT SUFFIX  
CASE 948G  
1
1
A
= Assembly Location  
WL, L = Wafer Lot  
= Year  
Features  
Y
WW, W = Work Week  
• High Speed: t = 3.8 ns (Typ) at V = 5.0 V  
PD  
CC  
G or G = Pb−Free Package  
• Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C  
CC  
A
(Note: Microdot may be in either location)  
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
See Applications Note #AND8004/D for  
date code and traceability information.  
• Power Down Protection Provided on Inputs  
• Balanced Propagation Delays  
• Designed for 2.0 V to 5.5 V Operating Range  
FUNCTION TABLE  
VHCT126A  
• Low Noise: V  
= 0.8 V (Max)  
OLP  
• Pin and Function Compatible with Other Standard Logic Families  
• Latchup Performance Exceeds 300 mA  
Inputs  
Outputs  
• ESD Performance: HBM > 2000 V; Machine Model > 200 V  
• Chip Complexity: 72 FETs or 18 Equivalent Gates  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
A
OE  
Y
H
L
X
H
H
L
H
L
Z
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
October, 2016 − Rev. 11  
MC74VHCT126A/D  
12345678

中文翻译

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M74VHCT126ADTR2G 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT126PW TI

类似代替

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
CD74HCT125M TI

功能相似

 High Speed CMOS Logic Quad Buffer, Three-State
CD74HCT125M96 TI

功能相似

 High-Speed CMOS Logic Quad Buffer, Three-State

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