Datasheet > M74VHC1G125DFT2G-L22038

M74VHC1G125DFT2G-L22038

更新时间： 2024-11-05 11:01:43

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
6页	138K
描述
Single Non-Inverting Buffer, 3-State

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M74VHC1G125DFT2G-L22038 数据手册

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MC74VHC1GT125

Noninverting Buffer /

CMOS Logic Level Shifter

with LSTTL−Compatible Inputs

The MC74VHC1GT125 is a single gate noninverting buffer

fabricated with silicon gate CMOS technology. It achieves high speed

operation similar to equivalent Bipolar Schottky TTL while

maintaining CMOS low power dissipation.

http://onsemi.com

MARKING

The MC74VHC1GT125 requires the 3−state control input (OE) to

be set High to place the output into the high impedance state.

The device input is compatible with TTL−type input thresholds and

the output has a full 5 V CMOS level output swing. The input protection

circuitry on this device allows overvoltage tolerance on the input,

allowing the device to be used as a logic−level translator from 3 V

CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V

CMOS Logic while operating at the high−voltage power supply.

The MC74VHC1GT125 input structure provides protection when

voltages up to 7 V are applied, regardless of the supply voltage. This

allows the MC74VHC1GT125 to be used to interface 5 V circuits to

3 V circuits. The output structures also provide protection when

DIAGRAMS

W1 M G

SC−88A / SOT−353 / SC−70

DF SUFFIX

CASE 419A

W1 M G

TSOP−5 / SOT−23 / SC−59

DT SUFFIX

= 0 V. These input and output structures help prevent device

destruction caused by supply voltage − input/output voltage mismatch,

battery backup, hot insertion, etc.

CASE 483

Features

= Device Code

= Date Code*

= Pb−Free Package

• High Speed: t = 3.5 ns (Typ) at V = 5 V

• Low Power Dissipation: I = 1 mA (Max) at T = 25°C

• TTL−Compatible Inputs: V = 0.8 V; V = 2 V

• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load

(Note: Microdot may be in either location)

*Date Code orientation and/or position may vary

depending upon manufacturing location.

CC OL

• Power Down Protection Provided on Inputs and Outputs

• Balanced Propagation Delays

• Pin and Function Compatible with Other Standard Logic Families

• Chip Complexity: FETs = 62; Equivalent Gates = 16

• These Devices are Pb−Free and are RoHS Compliant

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

PIN ASSIGNMENT

IN A

GND

OUT Y

IN A

GND

FUNCTION TABLE

OE Input

A Input

Y Output

OUT Y

Figure 1. Pinout (Top View)

IN A

OUT Y

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

Figure 2. Logic Symbol

Publication Order Number:

September, 2012 − Rev. 14

MC74VHC1GT125/D

12 3 4 5 6

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与M74VHC1G125DFT2G-L22038相关器件

型号	品牌	获取价格	描述	数据表
M74VHC1G125DTT1G	ONSEMI	获取价格	Noninverting 3−State Buffer
M74VHC1G126DFT1G	ONSEMI	获取价格	Noninverting 3−State Buffer
M74VHC1G126DFT2G	ONSEMI	获取价格	Noninverting 3−State Buffer
M74VHC1G126DFT2G-L22038	ONSEMI	获取价格	Single Non-Inverting Buffer, 3-State
M74VHC1G126DTT1G	ONSEMI	获取价格	Noninverting 3−State Buffer
M74VHC1G132DFT1G	ONSEMI	获取价格	2-Input NAND Schmitt-Trigger
M74VHC1G132DFT2G	ONSEMI	获取价格	2-Input NAND Schmitt-Trigger
M74VHC1G132DFT2G-L22038	ONSEMI	获取价格	单 2 输入 NAND 门极，带施密特触发器输入
M74VHC1G132DTT1G	ONSEMI	获取价格	2-Input NAND Schmitt-Trigger
M74VHC1G135DFT1G	ONSEMI	获取价格	2−Input NAND Schmitt−Trigger with Open Drain Output

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