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M74VHC1G125DTT1G PDF预览

M74VHC1G125DTT1G

更新时间: 2024-11-29 04:17:59
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管PC
页数 文件大小 规格书
6页 80K
描述
Noninverting 3−State Buffer

M74VHC1G125DTT1G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSOP
包装说明:TSOP-5针数:5
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.24
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:224842Samacsys Pin Count:5
Samacsys Part Category:Integrated CircuitSamacsys Package Category:SOT23 (5-Pin)
Samacsys Footprint Name:TSOP-5 CASE 483-02Samacsys Released Date:2015-08-04 10:24:16
Is Samacsys:N控制类型:ENABLE LOW
系列:AHC/VHCJESD-30 代码:R-PDSO-G5
JESD-609代码:e3长度:3 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE包装方法:TR
峰值回流温度(摄氏度):260电源:2/5.5 V
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):16 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:1.5 mm
Base Number Matches:1

M74VHC1G125DTT1G 数据手册

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MC74VHC1G125  
Noninverting 3−State Buffer  
The MC74VHC1G125 is an advanced high speed CMOS  
noninverting 3−state buffer fabricated with silicon gate CMOS  
technology. It achieves high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining CMOS low power  
dissipation.  
The internal circuit is composed of three stages, including a buffered  
3−state output which provides high noise immunity and stable output.  
The MC74VHC1G125 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1G125 to be used to interface 5 V circuits to 3 V  
circuits.  
http://onsemi.com  
MARKING  
DIAGRAMS  
5
5
W0 M G  
1
G
SC−88A/SOT−353/SC−70  
DF SUFFIX  
Features  
1
CASE 419A  
High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
Power Down Protection Provided on Inputs  
5
5
Balanced Propagation Delays  
W0 M G  
G
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 58; Equivalent Gates = 15  
Pb−Free Packages are Available  
1
1
TSOP−5/SOT−23/SC−59  
DT SUFFIX  
CASE 483  
W0 = Device Code  
M
G
= Date Code*  
= Pb−Free Package  
1
2
3
5
V
CC  
OE  
IN A  
GND  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
PIN ASSIGNMENT  
4
OUT Y  
1
2
3
4
5
OE  
IN A  
Figure 1. Pinout (Top View)  
GND  
OUT Y  
V
CC  
OE  
IN A  
FUNCTION TABLE  
OE Input  
EN  
OUT Y  
A Input  
Y Output  
L
H
X
L
L
L
H
Z
Figure 2. Logic Symbol  
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
February, 2007 − Rev. 15  
MC74VHC1G125/D  

M74VHC1G125DTT1G 替代型号

型号 品牌 替代类型 描述 数据表
MC74VHC1G125DFT1G ONSEMI

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Noninverting 3-State Buffer
74AHC1G125DCKRG4 TI

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