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M74HC4514TTR PDF预览

M74HC4514TTR

更新时间: 2024-11-02 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 291K
描述
4 TO 16 LINE DECODER/LATCH

M74HC4514TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.41
系列:HC/UH输入调节:STANDARD
JESD-30 代码:R-PDSO-G24长度:7.8 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A功能数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:2/6 VProp。Delay @ Nom-Sup:56 ns
传播延迟(tpd):230 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

M74HC4514TTR 数据手册

 浏览型号M74HC4514TTR的Datasheet PDF文件第2页浏览型号M74HC4514TTR的Datasheet PDF文件第3页浏览型号M74HC4514TTR的Datasheet PDF文件第4页浏览型号M74HC4514TTR的Datasheet PDF文件第5页浏览型号M74HC4514TTR的Datasheet PDF文件第6页浏览型号M74HC4514TTR的Datasheet PDF文件第7页 
M74HC4514  
4 TO 16 LINE DECODER/LATCH  
HIGH SPEED:  
= 20 ns (TYP.) at V  
t
= 6V  
CC  
PD  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
T & R  
V
CC  
DIP  
SOP  
M74HC4514B1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 4514  
M74HC4514M1R M74HC4514RM13TR  
M74HC4514TTR  
TSSOP  
DESCRIPTION  
The M74HC4514 is an high speed CMOS 4 LINE  
TO 16 LINE SEGMENT DECODER WITH  
LATCHED INPUTS fabricated with silicon gate  
available. The data applied to the data inputs are  
transferred to the Q outputs of latches when the  
strobe input is held high. When the strobe input is  
taken low, the information data applied to the data  
input at a time is retained at the output of the  
latches.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
C MOS technology.  
A binary code stored in the four input latches (A to  
D) provides a high level at the selected one of  
sixteen outputs excluding the other fifteen outputs,  
when the inhibit input (INHIBIT) is held low. When  
the inhibit input (INHIBIT) is held high, all outputs  
are kept low level, while the latch function is  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2003  
1/12  

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暂无描述
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