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M74HC4515RM13TR PDF预览

M74HC4515RM13TR

更新时间: 2024-11-24 21:13:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动双倍数据速率光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
10页 77K
描述
HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO24, SOP-24

M74HC4515RM13TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP24,.4
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84其他特性:ADDRESS LATCHES
系列:HC/UH输入调节:STANDARD
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.004 A
功能数量:1端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:2/6 V
Prop。Delay @ Nom-Sup:56 ns传播延迟(tpd):230 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

M74HC4515RM13TR 数据手册

 浏览型号M74HC4515RM13TR的Datasheet PDF文件第2页浏览型号M74HC4515RM13TR的Datasheet PDF文件第3页浏览型号M74HC4515RM13TR的Datasheet PDF文件第4页浏览型号M74HC4515RM13TR的Datasheet PDF文件第5页浏览型号M74HC4515RM13TR的Datasheet PDF文件第6页浏览型号M74HC4515RM13TR的Datasheet PDF文件第7页 
M74HC4515  
4 TO 16 LINE DECODER/LATCH (INV.)  
HIGH SPEED:  
= 20 ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
T & R  
V
CC  
DIP  
SOP  
M74HC4515B1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 4515  
M74HC4515M1R M74HC4515RM13TR  
M74HC4515TTR  
TSSOP  
DESCRIPTION  
The M74HC4515 is an high speed CMOS 4 LINE  
TO 16 LINE SEGMENT DECODER WITH  
LATCHED INPUTS fabricated with silicon gate  
available. The data applied to the data inputs are  
transferred to the Q outputs of latches when the  
strobe input is held high. When the strobe input is  
taken low, the information data applied to the data  
input at a time is retained at the output of the  
latches.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
C MOS technology.  
A binary code stored in the four input latches (A to  
D) provides a low level at the selected one of  
sixteen outputs excluding the other fifteen outputs,  
when the inhibit input (INHIBIT) is held low. When  
the inhibit input(INHIBIT) is held high, all outputs  
are kept high level, while the latch function is  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/10  

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