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M74HC4518TTR PDF预览

M74HC4518TTR

更新时间: 2024-11-24 05:10:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
11页 362K
描述
DUAL DECADE COUNTER

M74HC4518TTR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.55Is Samacsys:N
其他特性:GATED CLOCK; SCHMITT TRIGGER ON CLOCK INPUT计数方向:UP
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:DECADE COUNTER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A工作模式:SYNCHRONOUS
位数:4功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):240 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:24 MHzBase Number Matches:1

M74HC4518TTR 数据手册

 浏览型号M74HC4518TTR的Datasheet PDF文件第2页浏览型号M74HC4518TTR的Datasheet PDF文件第3页浏览型号M74HC4518TTR的Datasheet PDF文件第4页浏览型号M74HC4518TTR的Datasheet PDF文件第5页浏览型号M74HC4518TTR的Datasheet PDF文件第6页浏览型号M74HC4518TTR的Datasheet PDF文件第7页 
M74HC4518  
DUAL DECADE COUNTER  
HIGH SPEED :  
= 60 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
T & R  
V
CC  
DIP  
SOP  
M74HC4518B1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 4518  
M74HC4518M1R M74HC4518RM13TR  
M74HC4518TTR  
TSSOP  
DESCRIPTION  
The M74HC4518 is an high speed CMOS DUAL  
BINARY COUNTER fabricated with silicon gate  
C MOS technology.  
each positive-going transition of the CLOCK. The  
counters are cleared by high levels on their clear  
lines.  
2
It consist of two identical internally synchronous  
4-stage counters. The counter stages are D-TYPE  
flip-flops having interchangeable CLOCK and  
ENABLE inputs for incrementing on either the  
positive-going or negative-going transition.  
The counter can be cascaded in the ripple mode  
by connecting Q4 to the enable input of the  
subsequent counter while the clock input of the  
latter is held permanently low.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
For single-unit operation the ENABLE input is  
maintained "high" and the counter advances on  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

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