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M74HC4518B1R PDF预览

M74HC4518B1R

更新时间: 2024-11-26 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
13页 272K
描述
HC4518 DUAL DECADE COUNTER HC4520 DUAL 4 BIT BINARY COUNTER

M74HC4518B1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:7.51其他特性:GATED CLOCK; SCHMITT TRIGGER ON CLOCK INPUT
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDIP-T16JESD-609代码:e4
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:DECADE COUNTER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A工作模式:SYNCHRONOUS
位数:4功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):240 ns认证状态:Not Qualified
座面最大高度:5.1 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:24 MHz
Base Number Matches:1

M74HC4518B1R 数据手册

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M54/M74HC4518  
M54/M74HC4520  
HC4518 DUAL DECADE COUNTER  
HC4520 DUAL 4 BIT BINARY COUNTER  
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HIGH SPEED  
fMAX = 55 MHz (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
4520B/4518B  
ORDER CODES :  
M54HCXXXXF1R  
M74HCXXXXB1R  
M74HCXXXXM1R  
M74HCXXXXC1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC4518/4520 are high speed CMOS  
DUAL 4 BIT BINARY COUNTERS fabricated in sili-  
con gate C2MOS technology. They have the same  
high speed performance of LSTTL combined with  
true CMOS low power consumption.  
They consists of two identical internally syn-  
chronous 4-stage counters. The counter stages are  
D-type flip-flops having interchangeable Clock and  
ENABLE inputs for incrementing on either the posi-  
tive-going or negative-going transition.  
For single-unit operation the ENABLE input is main-  
tained ”high” and the counter advances on each  
positive-going transition of the CLOCK. The  
counters are cleared by high levels on their clear  
lines. The counter can be cascaded in the ripple  
mode by connecting Q4 to the enable input of the  
subsequent counter whilethe clock input ofthe latter  
is held permanently low.  
NC =  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
No Internal  
Connection  
March 1993  
1/13  

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