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M74HC4515 PDF预览

M74HC4515

更新时间: 2024-11-02 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
12页 291K
描述
HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH (INV.)

M74HC4515 数据手册

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M74HC4514  
4 TO 16 LINE DECODER/LATCH  
HIGH SPEED:  
= 20 ns (TYP.) at V  
t
= 6V  
CC  
PD  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
T & R  
V
CC  
DIP  
SOP  
M74HC4514B1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 4514  
M74HC4514M1R M74HC4514RM13TR  
M74HC4514TTR  
TSSOP  
DESCRIPTION  
The M74HC4514 is an high speed CMOS 4 LINE  
TO 16 LINE SEGMENT DECODER WITH  
LATCHED INPUTS fabricated with silicon gate  
available. The data applied to the data inputs are  
transferred to the Q outputs of latches when the  
strobe input is held high. When the strobe input is  
taken low, the information data applied to the data  
input at a time is retained at the output of the  
latches.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
C MOS technology.  
A binary code stored in the four input latches (A to  
D) provides a high level at the selected one of  
sixteen outputs excluding the other fifteen outputs,  
when the inhibit input (INHIBIT) is held low. When  
the inhibit input (INHIBIT) is held high, all outputs  
are kept low level, while the latch function is  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2003  
1/12  

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