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M74HC112_01 PDF预览

M74HC112_01

更新时间: 2024-11-23 05:10:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
12页 410K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC112_01 数据手册

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M74HC112  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED :  
= 79MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC112B1R  
M74HC112M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 112  
M74HC112RM13TR  
M74HC112TTR  
TSSOP  
DESCRIPTION  
The M74HC112 is an high speed CMOS DUAL  
J-K FLIP-FLOP WITH PRESET AND CLEAR  
fabricated with silicon gate C MOS technology.  
The M74HC112 dual JK flip-flop features  
individual J, K, clock, and asynchronous set and  
clear inputs for each flip-flop. When the clock goes  
high, the inputs are enabled and data will be  
accepted. The logic level of the J and K inputs  
may be allowed to change when the clock pulse is  
high and the bistable will function as shown in the  
truth table. Input data is transferred to the input on  
the negative going edge of the clock pulse.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/12  

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