M74HC113B1R

更新时间： 2024-11-24 22:46:35

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器
页数	文件大小	规格书
11页	250K
描述
DUAL J-K FLIP FLOP WITH PRESET

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中文翻译

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数据手册

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M74HC113B1R 数据手册

M54HC113

M74HC113

DUAL J-K FLIP FLOP WITH PRESET

HIGH SPEED

f_MAX= 71 MHz (TYP.) at V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 2 µA at T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

|I_OH| = I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V to 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS113

ORDER CODES :

M54HC113F1R

M74HC113B1R

M74HC113M1R

M74HC113C1R

DESCRIPTION

The M54/74HC113 is a high speed CMOS DUAL J-

K FLIP FLOP WITH PRESET fabricated in silicon

gate C2MOS technology. It has the same high

speed performance of LSTTL combined with true

CMOS lowpower consumption. Thiscircuit offersin-

dividual J, K, set, and clock inputs. Thesemonolithic

dual flip-flops are designed so that when the clock

goes HIGH, the inputs are enabled and data will be

accepted. The logic level of the J and K inputs may

be allowed to change when the clock pulse is HIGH

and the bistable will function as shown in the truth

table as long as minimum set-up times are ob-

served. Input data is transferred to the outputs on

the negative-going edge ofthe clock pulse. Allinputs

are equipped with protection circuits against static

discharge and transient excess voltage.

PIN CONNECTIONS (top view)

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

October 1992

1/11

12 3 4 5 6 7...11

中文翻译

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