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M59DR008E PDF预览

M59DR008E

更新时间: 2024-11-12 22:17:43
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意法半导体 - STMICROELECTRONICS 闪存
页数 文件大小 规格书
37页 268K
描述
8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory

M59DR008E 数据手册

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M59DR008E  
M59DR008F  
8 Mbit (512Kb x16, Dual Bank, Page) Low Voltage Flash Memory  
PRODUCT PREVIEW  
SUPPLY VOLTAGE  
– V  
= V  
= 1.65V to 2.2V: for Program,  
DDQ  
DD  
Erase and Read  
– V  
= 12V: optional Supply Voltage for fast  
PP  
Program and Erase  
ASYNCHRONOUS PAGE MODE READ  
– Page Width: 4 words  
BGA  
– Page Access: 35ns  
– Random Access: 100ns  
TSOP48 (N)  
12 x 20mm  
FBGA48 (ZB)  
8 x 6 solder balls  
PROGRAMMING TIME  
– 10µs by Word typical  
– Double Word Programming Option  
MEMORY BLOCKS  
– Dual Bank Memory Array: 4 Mbit - 4 Mbit  
– Parameter Blocks (Top or Bottom location)  
– Main Blocks  
Figure 1. Logic Diagram  
DUAL BANK OPERATIONS  
– Read within one Bank while Program or  
Erase within the other  
V
V
V
DD DDQ PP  
– No delay between Read and Write operations  
BLOCK PROTECTION/UNPROTECTION  
– All Blocks protected at Power Up  
19  
16  
A0-A18  
DQ0-DQ15  
– Any combination of Blocks can be protected  
– WP for Block Locking  
W
E
M59DR008E  
M59DR008F  
COMMON FLASH INTERFACE (CFI)  
64 bit SECURITY CODE  
G
RP  
WP  
ERASE SUSPEND and RESUME MODES  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
20 YEARS DATA RETENTION  
– Defectivity below 1ppm/year  
ELECTRONIC SIGNATURE  
– Manufacturer Code: 20h  
V
SS  
AI03212  
– Device Code, M59DR008E: A2h  
– Device Code, M59DR008F: A3h  
October 1999  
1/37  
This is preliminary information on a new product now in development. Details are subject to change without notice.  

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