Datasheet > M12L64164A-6BIG2M

M12L64164A-6BIG2M

更新时间： 2024-01-26 02:24:47

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
45页	1259K
描述
Synchronous DRAM, 4MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, VBGA-54

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M12L64164A-6BIG2M 数据手册

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ESMT

M12L64164A (2M)

Operation Temperature Condition -40°C~85°C

AC OPERATING TEST CONDITIONS (V_DD= 3.3V ± 0.3V ，T_A= -40 to 85 °C )

PARAMETER

Input levels (Vih/Vil)

VALUE

2.4/0.4

1.4

UNIT

Input timing measurement reference level

Input rise and fall-time

tr/tf = 1/1

1.4

Output timing measurement reference level

Output load condition

See Fig. 2

Vtt = 1.4V

3.3V

1200

Ω

VOH (DC) =2.4V , IOH = -2 mA

V^OL(DC) =0.4V , IOL = 2 mA

Output

^{Z0 =50}Ω

50pF

870

Ω

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

VERSION

PARAMETER

SYMBOL

UNIT

-7

NOTE

-5

-6

Row active to row active delay

t_RRD(min)

_RCD(min)

RAS to CAS delay

Row precharge time

t_RP(min)

t_RAS(min)

t_RAS(max)

100

Row active time

_RC(min)

@ Operating

Row cycle time

@ Auto refresh

1,5

_RFC(min)

Last data in to col. address delay

Last data in to row precharge

Last data in to burst stop

t_CDL(min)

t_RDL(min)

t_BDL(min)

t_CCD(min)

CLK

Col. address to col. address delay

CAS latency = 3

CAS latency = 2

Number of valid

Output data

Note:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer.

2. Minimum delay is required to complete with.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. A new command may be given t_RFCafter self refresh exit.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jun. 2012

Revision: 1.2 5/45

1 2 3 456 7 8...45

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