Datasheet > 存储 > DRAM> M12L64164A-6TA

M12L64164A-6TA

更新时间： 2024-02-27 02:49:05

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
44页	811K
描述
1M x 16 Bit x 4 Banks Synchronous DRAM

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M12L64164A-6TA 数据手册

ESMT

M12L64164A

Operation temperature condition -25℃ ~ 85℃

SDRAM

1M x 16 Bit x 4 Banks

Synchronous DRAM

FEATURES

ORDERING INFORMATION

54 Pin TSOP (Type II)

(400mil x 875mil )

ꢀ

JEDEC standard 3.3V power supply

LVTTL compatible with multiplexed address

Four banks operation

PRODUCT NO.

M12L64164A-6TA

M12L64164A-7TA

MAX FREQ.

166MHz

PACKAGE

MRS cycle with address key programs

- CAS Latency (2 & 3)

TSOP II

- Burst Length (1, 2, 4, 8 & full page)

- Burst Type (Sequential & Interleave)

All inputs are sampled at the positive going edge of the

system clock

143MHz

ꢀ

DQM for masking

Auto & self refresh

15.6 µ s refresh interval

GENERAL DESCRIPTION

The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by

16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high performance memory system applications.

PIN ASSIGNMENT

Top View

V^SS

V^DD

DQ0

V^DDQ

DQ1

DQ2

V^SSQ

DQ3

DQ4

V^DDQ

DQ5

DQ6

V^SSQ

DQ7

V^DD

LDQM

CAS

RAS

A¹³

A12

A10/AP

A⁰

DQ15

V^SSQ

DQ14

DQ13

V^DDQ

DQ12

DQ11

V^SSQ

DQ10

DQ9

V^DDQ

DQ8

V^SS

UDQM

CLK

CKE

A¹¹

VDD

VSS

Elite Semiconductor Memory Technology Inc.

Publication Date: Dec. 2004

Revision: 0.1 1/44

12 3 4 5 6 7...44

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