Electrical Specifications SuLbjTecCt to2C1ha9ng2e
LTC2191/LTC2190
16-Bit, 65Msps/40Msps/
25Msps Low Power
Dual ADCs
FEATURES
DESCRIPTION
The LTC®2192/LTC2191/LTC2190 are 2-channel, simul-
taneous sampling 16-bit A/D converters designed for
digitizinghighfrequency,widedynamicrangesignals.They
are perfect for demanding communications applications
with AC performance that includes 77dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
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2-Channel Simultaneous Sampling ADC
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Serial LVDS Outputs: 1, 2 or 4 Bits per Channel
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77dB SNR
90dB SFDR
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Low Power: 198mW/146mW/104mW Total
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99mW/73mW/ꢀ2mW per Channel
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Single 1.8V Supply
0.07ps
allows undersampling of IF frequencies with
RMS
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Selectable Input Ranges: 1V to 2V
excellent noise performance.
P-P
P-P
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ꢀꢀ0MHz Full-Power Bandwidth S/H
DC specs include 2LSB INL (typ), 0.ꢀLSB DNL (typ)
and no missing codes over temperature. The transition
Shutdown and Nap Modes
Serial SPI Port for Configuration
ꢀ2-Pin (7mm × 8mm) QFN Package
noise is 3.3LSB
.
RMS
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit, two bits or
four bits at a time. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
APPLICATIONS
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Communications
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Cellular Base Stations
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+
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Software-Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
The ENC and ENC inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
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Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
2-Tone FFT, fIN = 70MHz and 69MHz
0
–10
–20
–30
–40
–50
1.8V
1.8V
OV
V
DD
DD
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
CH1
ANALOG
INPUT
16-BIT
ADC CORE
S/H
S/H
CH2
ANALOG
INPUT
–60
–70
SERIALIZED
LVDS
OUTPUTS
16-BIT
ADC CORE
DATA
SERIALIZER
–80
–90
–100
–110
–120
ENCODE
INPUT
PLL
DATA CLOCK OUT
FRAME
GND
OGND
0
20
10
FREQUENCY (MHz)
30
219210 TA01a
219210 G07
219210p
1