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LP2995MX PDF预览

LP2995MX

更新时间: 2024-11-04 22:35:47
品牌 Logo 应用领域
美国国家半导体 - NSC 稳压器双倍数据速率
页数 文件大小 规格书
13页 290K
描述
DDR Termination Regulator

LP2995MX 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOP-8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5差分输出:NO
接口集成电路类型:BUS TERMINATOR SUPPORT CIRCUITJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
湿度敏感等级:1功能数量:1
端子数量:8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):235
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:5.5 V最小供电电压:2.2 V
标称供电电压:2.5 V表面贴装:YES
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

LP2995MX 数据手册

 浏览型号LP2995MX的Datasheet PDF文件第2页浏览型号LP2995MX的Datasheet PDF文件第3页浏览型号LP2995MX的Datasheet PDF文件第4页浏览型号LP2995MX的Datasheet PDF文件第5页浏览型号LP2995MX的Datasheet PDF文件第6页浏览型号LP2995MX的Datasheet PDF文件第7页 
July 2003  
LP2995  
DDR Termination Regulator  
General Description  
Features  
n Low output voltage offset  
n Works with +5v, +3.3v and 2.5v rails  
n Source and sink current  
n Low external component count  
n No external resistors required  
n Linear topology  
The LP2995 linear regulator is designed to meet the JEDEC  
SSTL-2 and SSTL-3 specifications for termination of DDR-  
SDRAM. The device contains a high-speed operational am-  
plifier to provide excellent response to load transients. The  
output stage prevents shoot through while delivering 1.5A  
continuous current and transient peaks up to 3A in the  
application as required for DDR-SDRAM termination. The  
LP2995 also incorporates a VSENSE pin to provide superior  
load regulation and a VREF output as a reference for the  
chipset and DDR DIMMS.  
n Available in SO-8, PSOP-8 or LLP-16 packages  
n Low cost and easy to use  
Applications  
n DDR Termination Voltage  
n SSTL-2  
Patents Pending  
n SSTL-3  
Typical Application Circuit  
20039302  
© 2003 National Semiconductor Corporation  
DS200393  
www.national.com  

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