LP2996-N
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SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013
LP2996-N DDR Termination Regulator
Check for Samples: LP2996-N
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FEATURES
DESCRIPTION
The LP2996-N linear regulator is designed to meet
the JEDEC SSTL-2 specifications for termination of
DDR-SDRAM. The device contains a high-speed
operational amplifier to provide excellent response to
load transients. The output stage prevents shoot
through while delivering 1.5A continuous current and
transient peaks up to 3A in the application as
required for DDR-SDRAM termination. The LP2996-N
also incorporates a VSENSE pin to provide superior
load regulation and a VREF output as a reference for
the chipset and DIMMs.
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Source and Sink Current
Low Output Voltage Offset
No External Resistors Required
Linear Topology
Suspend to Ram (STR) Functionality
Low External Component Count
Thermal Shutdown
Available in SOIC-8, SO PowerPAD-8 or
WQFN-16 packages
An additional feature found on the LP2996-N is an
active low shutdown (SD) pin that provides Suspend
To RAM (STR) functionality. When SD is pulled low
APPLICATIONS
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DDR-I and DDR-II Termination Voltage
SSTL-2 and SSTL-3 Termination
HSTL Termination
the VTT output will tri-state providing
a
high
impedance output, but, VREF will remain active. A
power savings advantage can be obtained in this
mode through lower quiescent current.
Typical Application Circuit
LP2996
VREF = 1.25V
VREF
SD
SD
+
0.01mF
220mF
VDDQ
VDDQ = 2.5V
VDD = 2.5V
VSENSE
AVIN
PVIN
VTT
VTT = 1.25V
+
+
GND
47mF
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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