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LP2996MRX PDF预览

LP2996MRX

更新时间: 2024-11-06 12:19:07
品牌 Logo 应用领域
德州仪器 - TI 总线通信稳压器驱动程序和接口接口集成电路光电二极管双倍数据速率
页数 文件大小 规格书
26页 1472K
描述
LP2996-N DDR Termination Regulator

LP2996MRX 技术参数

生命周期:Not Recommended零件包装代码:SOIC
包装说明:HLSOP,针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5Is Samacsys:N
差分输出:NO接口集成电路类型:BUS TERMINATOR SUPPORT CIRCUIT
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm湿度敏感等级:3
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HLSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, LOW PROFILE
峰值回流温度(摄氏度):260座面最大高度:1.68 mm
最大供电电压:5.5 V最小供电电压:2.2 V
标称供电电压:2.5 V表面贴装:YES
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

LP2996MRX 数据手册

 浏览型号LP2996MRX的Datasheet PDF文件第2页浏览型号LP2996MRX的Datasheet PDF文件第3页浏览型号LP2996MRX的Datasheet PDF文件第4页浏览型号LP2996MRX的Datasheet PDF文件第5页浏览型号LP2996MRX的Datasheet PDF文件第6页浏览型号LP2996MRX的Datasheet PDF文件第7页 
LP2996-N  
www.ti.com  
SNOSA40J NOVEMBER 2002REVISED MARCH 2013  
LP2996-N DDR Termination Regulator  
Check for Samples: LP2996-N  
1
FEATURES  
DESCRIPTION  
The LP2996-N linear regulator is designed to meet  
the JEDEC SSTL-2 specifications for termination of  
DDR-SDRAM. The device contains a high-speed  
operational amplifier to provide excellent response to  
load transients. The output stage prevents shoot  
through while delivering 1.5A continuous current and  
transient peaks up to 3A in the application as  
required for DDR-SDRAM termination. The LP2996-N  
also incorporates a VSENSE pin to provide superior  
load regulation and a VREF output as a reference for  
the chipset and DIMMs.  
2
Source and Sink Current  
Low Output Voltage Offset  
No External Resistors Required  
Linear Topology  
Suspend to Ram (STR) Functionality  
Low External Component Count  
Thermal Shutdown  
Available in SOIC-8, SO PowerPAD-8 or  
WQFN-16 packages  
An additional feature found on the LP2996-N is an  
active low shutdown (SD) pin that provides Suspend  
To RAM (STR) functionality. When SD is pulled low  
APPLICATIONS  
DDR-I and DDR-II Termination Voltage  
SSTL-2 and SSTL-3 Termination  
HSTL Termination  
the VTT output will tri-state providing  
a
high  
impedance output, but, VREF will remain active. A  
power savings advantage can be obtained in this  
mode through lower quiescent current.  
Typical Application Circuit  
LP2996  
VREF = 1.25V  
VREF  
SD  
SD  
+
0.01mF  
220mF  
VDDQ  
VDDQ = 2.5V  
VDD = 2.5V  
VSENSE  
AVIN  
PVIN  
VTT  
VTT = 1.25V  
+
+
GND  
47mF  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2002–2013, Texas Instruments Incorporated  

LP2996MRX 替代型号

型号 品牌 替代类型 描述 数据表
LP2996MRX/NOPB TI

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