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LP2995MX/NOPB PDF预览

LP2995MX/NOPB

更新时间: 2024-11-06 02:58:27
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德州仪器 - TI 双倍数据速率光电二极管接口集成电路
页数 文件大小 规格书
22页 1234K
描述
DDR Termination Regulator

LP2995MX/NOPB 数据手册

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LP2995  
www.ti.com  
SNVS190M FEBRUARY 2002REVISED MARCH 2013  
LP2995 DDR Termination Regulator  
Check for Samples: LP2995  
1
FEATURES  
DESCRIPTION  
The LP2995 linear regulator is designed to meet the  
JEDEC SSTL-2 and SSTL-3 specifications for  
termination of DDR-SDRAM. The device contains a  
high-speed operational amplifier to provide excellent  
response to load transients. The output stage  
prevents shoot through while delivering 1.5A  
continuous current and transient peaks up to 3A in  
the application as required for DDR-SDRAM  
termination. The LP2995 also incorporates a VSENSE  
pin to provide superior load regulation and a VREF  
output as a reference for the chipset and DDR  
DIMMS.  
2
Low Output Voltage Offset  
Works with +5v, +3.3v and 2.5v Rails  
Source and Sink Current  
Low External Component Count  
No External Resistors Required  
Linear Topology  
Available in SOIC-8, SO PowerPAD-8 or  
WQFN-16 Packages  
Low Cost and Easy to Use  
WHITE SPACE  
WHITE SPACE  
WHITE SPACE  
WHITE SPACE  
APPLICATIONS  
DDR Termination Voltage  
SSTL-2  
SSTL-3  
Typical Application Circuit  
VREF = 1.25V  
+
LP2995  
0.1mF  
VDDQ = 2.5V  
VDD = 2.5V  
VDDQ  
AVIN  
PVIN  
VREF  
VSENSE  
VTT  
VTT = 1.25V  
+
+
GND  
50mF  
220mF  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2002–2013, Texas Instruments Incorporated  

LP2995MX/NOPB 替代型号

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