Datasheet > LM9630SAMPLE-KIT

LM9630SAMPLE-KIT

更新时间： 2024-11-23 22:26:27

品牌	Logo	应用领域
美国国家半导体 - NSC		传感器图像传感器
页数	文件大小	规格书
2页	81K
描述
LM9630 100 x 128, 580 fps Ultra Sensitive Monochrome CMOS Image Sensor

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中文翻译

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LM9630SAMPLE-KIT 数据手册

ADVANCE INFORMATION

May 2002

LM9630 100 x 128, 580 fps Ultra Sensitive Monochrome CMOS Image Sensor

General Description

Key Specifications

The LM9630 is a high performance, low power, CMOS Active

Pixel Image Sensor capable of capturing monochrome images

at 580 frames per second.

Array Format

Total

Active

128H x 101V

118H x 96V

In addition to the active pixel array, an on-chip 8 bit A/D conver-

tor, fixed pattern noise elimination circuits and a video gain

amplifier are provided.

Effective Image Area

Total

Active

2.56 mm x 2.00 mm

2.36 mm x 1.92 mm

The integrated programmable timing and control circuit allows

the user maximum flexibility in adjusting integration time and

frame rate. Furthermore, a fast read out circuit is provided allow-

ing a full frame to read out on a single 8-bit digital data bus in

less than 2ms.

Optical Format

Pixel Size

1/5”

20mm x 20mm

8 Bit Digital

580 frames per second

48 dB

Video Outputs

Frame Rate

Dynamic Range

Electronic Shutter

FPN

The sensor utilizes a patented pixel design that incorporates an

integrated electronic shutter. This together with its ultra high sen-

sitivity makes the LM9630 an ideal choice for low light imaging

applications or applications where images of fast moving objects

need to be captured with minimum motion blur.

Global Reset

0.5%

Applications

PRMU

1.3%

High Speed Motion Detection

IR Imaging

Low Light Imaging Applications

Sensitivity

22 Volt/lux.s

47%

Fill Factor

Package

32 CLCC

3.3V +/- 10%

110 mW

Features

Single Supply

Power Consumption

Operating Temp

Electronic shutter with global reset & pixel exposure.

Programmable analog video gain.

Integrated 8 bit analog to digital conversion.

Programmable integration time.

-40 C to 85 C

Programmable frame rate.

Master and slave mode of operation

On chip black level compensation.

Power down and low power modes.

I C compatible serial interface.

10 bit digital video port (8 data, vertical & horizontal sync).

Power on reset with hardware and software override.

Chip Block Diagram

mclk

reset

sda

sclk

Serial I/F

Clock Gen

Reset Gen

APS Array

Offset

Gain

POR

Column CDS

d[7:0]

hsync

vsync

Digital

Image Data

Framer

Shift

AMP

Bit A/D

Master Timer

ã 2002 National Semiconductor Corporation

www.national.com

中文翻译

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