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LM9637

更新时间: 2024-11-23 22:47:03
品牌 Logo 应用领域
美国国家半导体 - NSC 传感器图像传感器
页数 文件大小 规格书
2页 133K
描述
LM9637 Monochrome CMOS Image Sensor VGA 68 FPS

LM9637 数据手册

 浏览型号LM9637的Datasheet PDF文件第2页 
ADVANCE INFORMATION  
MAY 2002  
LM9637 Monochrome CMOS Image Sensor VGA 68 FPS  
General Description  
Applications  
The LM9637 is a high performance, low power, 1/4" VGA CMOS  
Active Pixel Sensor capable of capturing monochrome still or  
motion images and converting them to a digital data stream.  
f Security Camera  
f Machine Vision  
f Barcode Scanners  
f Biometrics  
Excellent image quality is achieved by integrating a high perfor-  
mance analog signal processor comprising of a high speed 10  
bit A/D convertor, fixed pattern noise elimination circuits and a  
programmable gain amplifier. The offset and black level can be  
automatically adjusted on chip using a full loop black level com-  
pensation circuit.  
Key Specifications  
Total: 488 x 672  
Active: 488 x 648  
Array Format  
Total: 2.93mm x 4.03mm  
Active: 2.93mm x 3.89mm  
Furthermore, a programmable smart timing and control circuit  
allowing the user maximum flexibility in adjusting integration  
time, active window size, gain, frame rate. Various control, tim-  
ing and power modes are also provided.  
Effective Image Area  
Optical Format  
Pixel Size  
1/4"  
6.0mm x 6.0mm  
8 & 10 Bit Digital  
68 frames per second  
57 dB  
Video Outputs  
Frame Rate  
Dynamic Range  
Electronic Shutter  
FPN  
Features  
f Master and slave mode operation  
f Progressive scan read out with horizontal and vertical flip  
f Programmable Exposure:  
Rolling Reset  
0.5%  
-
-
-
-
Master clock divider  
Inter row delay  
Inter frame delay  
PRMU  
1.7%  
Partial frame integration  
Sensitivity  
2.40 volts/lux.s  
49%  
f Programmable gain amplifier  
f Full automatic servo loop for black level & offset adjustment  
on each gain channel  
f Horizontal & vertical sub-sampling (2:1 & 4:2) with averaging  
f Windowing  
Fill Factor  
Micro Lens  
none  
Package  
32 LCC  
f Programmable pixel clock, inter-frame and inter-line delays  
Single Supply  
Power Consumption  
Operating Temp  
3.0V +/-10%  
130mW  
2
f I C compatible serial control interface  
f Power on reset & power down mode  
o
o
-10 C to 50 C  
Overall Chip Block Diagram  
sclk sda sadr  
resetb  
POR  
pwd  
mclk  
2
APS Array  
I C Compatible  
Serial I/F  
Power  
Control  
Register  
Bank  
clk gen  
snapshot  
extsync  
Master Sensor Controller  
d[9:0]  
pclk  
+/-  
Amp  
10 bit A/D  
Column CDS  
hsync  
vsync  
Figure 1. Chip Block Diagram  
ã 2002 National Semiconductor Corporation  
www.national.com  

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