ADVANCE INFORMATION
May 2002
LM9647 Color CMOS Image Sensor VGA 68 FPS
General Description
Applications
The LM9647 is a high performance, low power, 1/4" VGA CMOS
Active Pixel Sensor capable of capturing color still or motion
images and converting them to a digital data stream.
f Dual Mode Camera
f Digital Still Camera
f Security Camera
f Machine Vision
Excellent image quality is achieved by integrating a high perfor-
mance analog signal processor comprising of a high speed 10
bit A/D convertor, fixed pattern noise elimination circuits and
separate color gain amplifiers. The offset and black level can be
automatically adjusted on chip using a full loop black level com-
pensation circuit.
Key Specifications
Total: 488 x 672
Active: 488 x 648
Array Format
Total: 2.93mm x 4.03mm
Active: 2.93mm x 3.89mm
Furthermore, a programmable smart timing and control circuit
allowing the user maximum flexibility in adjusting integration
time, active window size, gain, frame rate. Various control, tim-
ing and power modes are also provided.
Effective Image Area
Optical Format
Pixel Size
1/4"
6.0mm x 6.0mm
8 & 10 Bit Digital
68 frames per second
57 dB
Video Outputs
Frame Rate
Dynamic Range
Electronic Shutter
FPN
Features
f Master and slave mode operation
f Progressive scan read out with horizontal and vertical flip
f Programmable Exposure:
Rolling Reset
0.5%
-
-
-
-
Master clock divider
Inter row delay
Inter frame delay
PRMU
1.7%
Partial frame integration
Sensitivity
2.5 volts/lux.s
49%
f Four channels of digitally programmable analog gain
f Full automatic servo loop for black level & offset adjustment
on each gain channel
f Horizontal & vertical sub-sampling (2:1 & 4:2) with averaging
f Windowing
Fill Factor
Color Mosaic
Package
Bayer pattern
32 LCC
f Programmable pixel clock, inter-frame and inter-line delays
Single Supply
Power Consumption
Operating Temp
3.0V +/-10%
130mW
2
f I C compatible serial control interface
f Power on reset & power down mode
o
o
-10 C to 50 C
Overall Chip Block Diagram
sclk sda sadr
resetb
POR
pwd
mclk
2
APS Array
I C Compatible
Serial I/F
Power
Control
Register
Bank
clk gen
snapshot
extsync
Master Sensor Controller
+/-
+/-
+/-
+/-
ch0
d[9:0]
pclk
ch1
ch2
ch3
MUX
10 bit A/D
Column CDS
hsync
vsync
Figure 1. Chip Block Diagram
ã 2002 National Semiconductor Corporation
www.national.com