Datasheet > KSZ8895MQXC-TR

KSZ8895MQXC-TR

更新时间： 2024-11-16 00:42:59

品牌	Logo	应用领域
美国微芯 - MICROCHIP		局域网（LAN）标准以太网：16GBASE-T 电信电信集成电路
页数	文件大小	规格书
108页	1245K
描述
Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface

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技术参数
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KSZ8895MQXC-TR 技术参数

生命周期：	Active	包装说明：	QFP-128
Reach Compliance Code：	compliant	Factory Lead Time：	16 weeks
风险等级：	5.69	Is Samacsys：	N
JESD-30 代码：	R-PQFP-G128	长度：	20 mm
功能数量：	1	端子数量：	128
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, FINE PITCH
筛选级别：	TS 16949	座面最大高度：	3.4 mm
标称供电电压：	1.2 V	表面贴装：	YES
电信集成电路类型：	ETHERNET TRANSCEIVER	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

KSZ8895MQXC-TR 数据手册

KSZ8895MQX/RQX/FQX/MLX

Integrated 5-Port 10/100 Managed Ethernet

Switch with MII/RMII Interface

• Programmable Weighted Fair Queuing for Ratio

Control

Features

Advanced Switch Features

• Re-Mapping of 802.1p Priority Field Per Port

Basis

• IEEE 802.1q VLAN Support for up to 128 Active

VLAN Groups (Full-Range 4096 of VLAN IDs)

Integrated 5-Port 10/100 Ethernet Switch

• Static MAC Table Supports up to 32 Entries

• VLAN ID Tag/Untagged Options, Per Port Basis

• New Generation Switch with Five MACs and Five

PHYs that are Fully Compliant with the IEEE

802.3u Standard

• IEEE 802.1p/q Tag Insertion or Removal on a Per

Port Basis Based on Ingress Port (Egress)

• PHYs Designed with Patented Enhanced Mixed-

Signal Technology

• Programmable Rate Limiting at the Ingress and

Egress on a Per Port Basis

• Non-Blocking Switch Fabric Ensures Fast Packet

Delivery by Utilizing a 1K MAC Address Lookup

Table and a Store-and-Forward Architecture

• Jitter-Free Per Packet Based Rate Limiting Sup-

port

• Broadcast Storm Protection with Percentage Con-

trol (Global and Per Port Basis)

• On-Chip 64Kbyte Memory for Frame Buffering

(Not Shared with 1K Unicast Address Table)

• IEEE 802.1d Rapid Spanning Tree Protocol RSTP

Support

• Full-Duplex IEEE 802.3x Flow Control (PAUSE)

with Force Mode Option

• Tail Tag Mode (1 Byte Added Before FCS) Sup-

port at Port 5 to Inform the Processor Which

Ingress Port Receives the Packet

• Half-Duplex Back Pressure Flow Control

• HP Auto MDI/MDI-X and IEEE Auto Crossover

Support

• 1.4 Gbps High-Performance Memory Bandwidth

and Shared Memory Based Switch Fabric with

Fully Non-Blocking Configuration

• SW-MII Interface Supports Both MAC Mode and

PHY Mode

• 7-Wire Serial Network Interface (SNI) Support for

Legacy MAC

• Dual MII with MAC 5 and PHY 5 on Port 5, SW5-

MII/RMII for MAC 5 and P5-MII/RMII for PHY 5

• Per Port LED Indicators for Link, Activity, and 10/

100 Speed

• Enable/Disable Option for Huge Frame Size up to

2000 Bytes Per Frame

• Register Port Status Support for Link, Activity,

Full-/Half-Duplex and 10/100 Speed

• LinkMD^®Cable Diagnostic Capabilities

• IGMP v1/v2 Snooping (IPv4) Support for Multicast

Packet Filtering

• IPv4/IPv6 QoS Support

• On-Chip Terminations and Internal Biasing Tech-

nology for Cost Down and Lowest Power Con-

sumption

• Support Unknown Unicast/Multicast Address and

Unknown VID Packet Filtering

• Self-Address Filtering

Switch Monitoring Features

Comprehensive Configuration Register Access

• Port Mirroring/Monitoring/Sniffing: Ingress and/or

Egress Traffic to Any Port or MII

• Serial Management Interface (MDC/MDIO) to All

PHYs Registers and SMI Interface (MDC/MDIO)

to All Registers

• High-Speed SPI (up to 25 MHz) and I²C Master

Interface to all Internal Registers

• MIB Counters for Fully Compliant Statistics Gath-

ering; 34 MIB Counters Per Port

• Loopback Support for MAC, PHY, and Remote

Diagnostic of Failure

• I/O Pins Strapping and EEPROM to Program

Selective Registers in Unmanaged Switch Mode

• Interrupt for the Link Change on Any Ports

Low-Power Dissipation

• Control Registers Configurable on the Fly (Port-

Priority, 802.1p/d/q, AN…)

• Full-Chip Hardware Power-Down

• Full-Chip Software Power-Down and Per Port

Software Power-Down

QoS/CoS Packet Prioritization Support

• Per Port, 802.1p and DiffServ-Based

• Energy-Detect Mode Support <100 mW Full-Chip

Power Consumption When All Ports Have No

• 1/2/4-Queue QoS Prioritization Selection

 2016 Microchip Technology Inc.

DS00002246A-page 1

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与KSZ8895MQXC-TR相关器件

型号	品牌	获取价格	描述	数据表
KSZ8895MQXI	MICROCHIP	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface
KSZ8895MQXIA	MICROCHIP	获取价格	DATACOM, ETHERNET TRANSCEIVER, PQFP128
KSZ8895MQXI-TR	MICROCHIP	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface
KSZ8895RLXC	MICROCHIP	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface
KSZ8895RLXC-TR	MICROCHIP	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface
KSZ8895RLXI	MICROCHIP	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface
KSZ8895RLXI-TR	MICROCHIP	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface
KSZ8895RQ	MICREL	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
KSZ8895RQ	INFINEON	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
KSZ8895RQI	MICREL	获取价格	Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface

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