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KSZ8993ML-TR PDF预览

KSZ8993ML-TR

更新时间: 2024-11-06 15:44:51
品牌 Logo 应用领域
美国微芯 - MICROCHIP 局域网电信开关电信集成电路
页数 文件大小 规格书
74页 1603K
描述
Network Interface

KSZ8993ML-TR 技术参数

生命周期:Active包装说明:FQFP, QFP128,.68X.91,20
Reach Compliance Code:compliant风险等级:5.73
数据速率:100000 MbpsJESD-30 代码:R-PQFP-G128
长度:20 mm功能数量:1
端子数量:128收发器数量:2
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP128,.68X.91,20封装形状:RECTANGULAR
封装形式:FLATPACK, FINE PITCH座面最大高度:3.4 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:LAN SWITCHING CIRCUIT温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

KSZ8993ML-TR 数据手册

 浏览型号KSZ8993ML-TR的Datasheet PDF文件第2页浏览型号KSZ8993ML-TR的Datasheet PDF文件第3页浏览型号KSZ8993ML-TR的Datasheet PDF文件第4页浏览型号KSZ8993ML-TR的Datasheet PDF文件第5页浏览型号KSZ8993ML-TR的Datasheet PDF文件第6页浏览型号KSZ8993ML-TR的Datasheet PDF文件第7页 
KSZ8993M  
Integrated 3-Port 10/100 Managed Switch with PHYs  
- IGMP V1/V2 Snooping Support for Multicast  
Packet Filtering  
- Double-Tagging Support  
• Switch Management Features  
- Port Mirroring/Monitoring/Sniffing: Ingress and/  
or Egress Traffic to Any Port or MII  
- Management Information Base Counters for  
Fully Compliant Statistics Gathering, 34 MIB  
Counters Per Port  
Features  
• Integrated 3-Port 10/100 Ethernet Switch  
- 2nd Generation Switch with Three MACs and  
Two PHYs Fully Compliant to IEEE 802.3u  
Standard  
- Non-Blocking Switch Fabric Ensures Fast  
Packet Delivery by Utilizing a 1K MAC Address  
Lookup Table and a Store-and-Forward Archi-  
tecture  
- Loopback Modes for Remote Diagnostic of Fail-  
ure  
• Low Power Dissipation  
- <0.8 Watts (includes PHY transmit drivers)  
- Full-Chip Hardware Power-Down (Register  
Configuration Not Saved)  
- Per Port Based Software Power-Save on PHY  
(Idle Link Detection, Register Configuration Pre-  
served)  
- Full-Duplex IEEE 802.3x Flow Control (PAUSE)  
with Force Mode Option  
- Half-Duplex Back Pressure Flow Control  
- Automatic MDI/MDI-X Crossover with Disable  
and Enable Option  
- 100BASE-FX Support on Port 1  
- MII Interface Supports Both MAC Mode and  
PHY Mode  
- 7-Wire Serial Network Interface (SNI) Support  
for Legacy MAC  
- Comprehensive LED Indicator Support for Link,  
Activity, Full-/Half-Duplex and 10/100 Speed  
• Comprehensive Configuration Register Access  
- Serial Management Interface (SMI) to All Inter-  
nal Registers  
- Voltages: Core 1.8V, I/O and Transceiver 3.3V  
(Use KSZ8993ML for 3.3V-Only Operation)  
• Available in a 128-Pin PQFP Package  
Applications  
• Universal Solutions  
- Broadband Gateway/Firewall/VPN  
- Integrated DSL or Cable Modem Multi-Port  
Router  
- MII Management (MIIM) Interface to PHY Reg-  
isters  
- SPI and I C Interface to all internal registers  
2
- Wireless LAN Access Point + Gateway  
- Residential and Enterprise VoIP Gateway/  
Phone  
- I/O Pins Strapping and EEPROM to Program  
Selective Registers in Unmanaged Switch  
Mode  
- Set-Top/Game Box  
- Home Networking Expansion  
- Standalone 10/100 Switch  
- FTTx Customer Premises Equipment  
- Fiber Broadband Gateway  
• Upgradeable Solutions (Note 1)  
- Unmanaged Switch with Future Option to  
Migrate to a Managed Solution  
- Single PHY Alternative with Future Expansion  
Option for Two Ports  
- Control Registers Configurable on the Fly (Port-  
Priority, 802.1p/d/q, AN, etc.)  
• QoS/CoS Packet Prioritization Support  
- Per Port, 802.1p, and DiffServ-Based  
- Re-Mapping of 802.1p Priority Field Per Port  
Basis  
- Four Priority Levels  
• Advanced Switch Features  
- IEEE 802.1q VLAN Support for Up to 16 Groups  
(Full Range of VLAN IDs)  
• Industrial Solutions  
- Applications that Require Port Redundancy and  
Port Monitoring  
- VLAN ID Tag/Untag Options, Per Port Basis  
- IEEE 802.1p/q Tag Insertion or Removal on a  
Per Port Basis (Egress)  
- Sensor Devices in Redundant Ring Topology  
- Programmable Rate Limiting from 0 Mbps to  
100 Mbps at the Ingress and Egress Port, Rate  
Options for High and Low Priority Per Port Basis  
- Broadcast Storm Protection with Percent Con-  
trol (Global and Per Port Basis)  
Note 1: The cost and time of PCB re-spin.  
- IEEE 802.1d Spanning Tree Protocol Support  
- Upstream Special Tagging Mode to Inform the  
Processor which Ingress Port Receives the  
Packet  
2019 Microchip Technology Inc.  
DS00003066A-page 1  

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