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KSZ9021RLTR PDF预览

KSZ9021RLTR

更新时间: 2024-09-17 09:38:59
品牌 Logo 应用领域
美国微芯 - MICROCHIP 以太网:16GBASE-T电信电信集成电路
页数 文件大小 规格书
67页 552K
描述
Ethernet Transceiver

KSZ9021RLTR 技术参数

生命周期:Active包装说明:HLFQFP,
Reach Compliance Code:compliant风险等级:5.72
JESD-30 代码:S-PQFP-G64长度:10 mm
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
座面最大高度:1.6 mm标称供电电压:1.2 V
表面贴装:YES电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

KSZ9021RLTR 数据手册

 浏览型号KSZ9021RLTR的Datasheet PDF文件第2页浏览型号KSZ9021RLTR的Datasheet PDF文件第3页浏览型号KSZ9021RLTR的Datasheet PDF文件第4页浏览型号KSZ9021RLTR的Datasheet PDF文件第5页浏览型号KSZ9021RLTR的Datasheet PDF文件第6页浏览型号KSZ9021RLTR的Datasheet PDF文件第7页 
KSZ9021RL/RN  
Gigabit Ethernet Transceiver with RGMII Support  
Highlights  
Applications  
• Single-chip 10/100/1000Mbps IEEE 802.3 compli-  
ant Ethernet Transceiver  
• Laser/Network printer  
• Network attached storage (NAS)  
• Network server  
• RGMII interface compliant to RGMII Version 1.3  
• RGMII I/Os with 3.3V/2.5V tolerant and program-  
mable timings to adjust and correct delays on  
both Tx and Rx paths  
• Gigabit LAN on motherboard (GLOM)  
• Broadband gateway  
• Gigabit SOHO/SMB router  
• IPTV  
• Auto-negotiation to automatically select the high-  
est link up speed (10/100/100Mbps) and duplex  
(half/full)  
• IP Set-top box  
• Game console  
• On-chip termination resistors for the differential  
pairs  
• Triple-play (data, voice, video) media center  
• Media converter  
• On-chip LDO controller to support single 3.3V  
supply operation – requires only external FET to  
generate 1.2V for the core  
• Jumbo frame support up to 16KB  
• 125MHz Reference Clock Output  
• Programmable LED outputs for link, activity and  
speed  
• Baseline Wander Correction  
• LinkMD® TDR-based cable diagnostics for identi-  
fication of faulty copper cabling  
• Parametric NAND Tree support for fault detection  
between chip I/Os and board.  
• Loopback modes for diagnostics  
• Automatic MDI/MDI-X crossover for detection and  
correction of pair swap at all speeds of operation  
• Automatic detection and correction of pair swap,  
pair skew and pair polarity  
• MDC/MDIO Management Interface for PHY regis-  
ter configuration  
• Interrupt pin option  
• Power down and power saving modes  
• Operating Voltages  
- Core:  
- I/O:  
1.2V (external FET or regulator)  
3.3V or 2.5V  
- Transceiver: 3.3V  
• Available packages  
64-pin E-LQFP (10mm x 10mm): KSZ9021RL  
48-pin QFN (7mm x 7mm): KSZ9021RN  
2009-2019 Microchip Technology Inc.  
DS00003050A-page 1  

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