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KM48S16030BN-FH PDF预览

KM48S16030BN-FH

更新时间: 2024-11-01 13:01:19
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器
页数 文件大小 规格书
10页 120K
描述
Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54

KM48S16030BN-FH 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP,针数:54
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.84
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
JESD-30 代码:R-PDSO-G54长度:11.2 mm
内存密度:134217728 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:54
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

KM48S16030BN-FH 数据手册

 浏览型号KM48S16030BN-FH的Datasheet PDF文件第2页浏览型号KM48S16030BN-FH的Datasheet PDF文件第3页浏览型号KM48S16030BN-FH的Datasheet PDF文件第4页浏览型号KM48S16030BN-FH的Datasheet PDF文件第5页浏览型号KM48S16030BN-FH的Datasheet PDF文件第6页浏览型号KM48S16030BN-FH的Datasheet PDF文件第7页 
Preliminary  
KM48S16030  
CMOS SDRAM  
4M x 8Bit x 4 Banks Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
• JEDEC standard 3.3V power supply  
• LVTTL compatible with multiplexed address  
• Four banks operation  
The KM48S16030 is 134,217,728 bits synchronous high data  
rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits,  
fabricated with SAMSUNG¢s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock I/O transactions are possible on every clcok  
cycle. Range of operating frequencies, programmable burst  
length and programmable latencies allow the same device to be  
useful for a variety of high bandwidth, high performance mem-  
ory system applications.  
• MRS cycle with address key programs  
-. CAS Latency (2 & 3)  
-. Burst Length (1, 2, 4, 8 & full page)  
-. Burst Type (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst Read Single-bit Write operation  
• DQM for masking  
ORDERING INFORMATION  
• Auto & self refresh  
Part NO.  
MAX Freq. Interface Package  
• 64ms refresh period (4K cycle)  
KM48S16030T-G/F8  
KM48S16030T-G/FH  
KM48S16030T-G/FL  
KM48S16030T-G/F10  
125MHz  
54pin  
TSOP(II)  
100MHz  
100MHz  
100MHz  
LVTTL  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
4M x 8  
4M x 8  
4M x 8  
4M x 8  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
DQM  
Samsung Electronics reserves the right to  
change products or specification without  
notice.  
*
REV. 2 Mar. '98  

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Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54
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