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KM48S16030T-G/F10 PDF预览

KM48S16030T-G/F10

更新时间: 2024-11-05 22:19:51
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器
页数 文件大小 规格书
10页 120K
描述
4M x 8Bit x 4 Banks Synchronous DRAM

KM48S16030T-G/F10 数据手册

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Preliminary  
KM48S16030  
CMOS SDRAM  
4M x 8Bit x 4 Banks Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
• JEDEC standard 3.3V power supply  
• LVTTL compatible with multiplexed address  
• Four banks operation  
The KM48S16030 is 134,217,728 bits synchronous high data  
rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits,  
fabricated with SAMSUNG¢s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock I/O transactions are possible on every clcok  
cycle. Range of operating frequencies, programmable burst  
length and programmable latencies allow the same device to be  
useful for a variety of high bandwidth, high performance mem-  
ory system applications.  
• MRS cycle with address key programs  
-. CAS Latency (2 & 3)  
-. Burst Length (1, 2, 4, 8 & full page)  
-. Burst Type (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst Read Single-bit Write operation  
• DQM for masking  
ORDERING INFORMATION  
• Auto & self refresh  
Part NO.  
MAX Freq. Interface Package  
• 64ms refresh period (4K cycle)  
KM48S16030T-G/F8  
KM48S16030T-G/FH  
KM48S16030T-G/FL  
KM48S16030T-G/F10  
125MHz  
54pin  
TSOP(II)  
100MHz  
100MHz  
100MHz  
LVTTL  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
4M x 8  
4M x 8  
4M x 8  
4M x 8  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
DQM  
Samsung Electronics reserves the right to  
change products or specification without  
notice.  
*
REV. 2 Mar. '98  

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