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KM48S16030BT-FL PDF预览

KM48S16030BT-FL

更新时间: 2024-11-01 13:09:07
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器
页数 文件大小 规格书
10页 120K
描述
Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

KM48S16030BT-FL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP54,.46,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G54JESD-609代码:e0
长度:22.22 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:8
功能数量:1端口数量:2
端子数量:54字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
刷新周期:4096座面最大高度:1.2 mm
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.21 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

KM48S16030BT-FL 数据手册

 浏览型号KM48S16030BT-FL的Datasheet PDF文件第2页浏览型号KM48S16030BT-FL的Datasheet PDF文件第3页浏览型号KM48S16030BT-FL的Datasheet PDF文件第4页浏览型号KM48S16030BT-FL的Datasheet PDF文件第5页浏览型号KM48S16030BT-FL的Datasheet PDF文件第6页浏览型号KM48S16030BT-FL的Datasheet PDF文件第7页 
Preliminary  
KM48S16030  
CMOS SDRAM  
4M x 8Bit x 4 Banks Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
• JEDEC standard 3.3V power supply  
• LVTTL compatible with multiplexed address  
• Four banks operation  
The KM48S16030 is 134,217,728 bits synchronous high data  
rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits,  
fabricated with SAMSUNG¢s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock I/O transactions are possible on every clcok  
cycle. Range of operating frequencies, programmable burst  
length and programmable latencies allow the same device to be  
useful for a variety of high bandwidth, high performance mem-  
ory system applications.  
• MRS cycle with address key programs  
-. CAS Latency (2 & 3)  
-. Burst Length (1, 2, 4, 8 & full page)  
-. Burst Type (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst Read Single-bit Write operation  
• DQM for masking  
ORDERING INFORMATION  
• Auto & self refresh  
Part NO.  
MAX Freq. Interface Package  
• 64ms refresh period (4K cycle)  
KM48S16030T-G/F8  
KM48S16030T-G/FH  
KM48S16030T-G/FL  
KM48S16030T-G/F10  
125MHz  
54pin  
TSOP(II)  
100MHz  
100MHz  
100MHz  
LVTTL  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
4M x 8  
4M x 8  
4M x 8  
4M x 8  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
DQM  
Samsung Electronics reserves the right to  
change products or specification without  
notice.  
*
REV. 2 Mar. '98  

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