KK4017BD

更新时间： 2024-11-07 03:48:07

品牌	Logo	应用领域
可天士 - KODENSHI		计数器
页数	文件大小	规格书
7页	423K
描述
Counter/Divider

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中文翻译

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数据手册

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KK4017BD 数据手册

TECHNICAL DATA

KK4017B

Counter/Divider

The KK4017B is 5-stage Johnson counter having 10 decoded outputs.

Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal.

Schmitt trigger action in the CLOCK input circuit provides pulse shaping

that allows unlimited clock input pulse rise and fall times.

N SUFFIX

PLASTIC

The counter is advanced one count at the positive clock signal

transition if the CLOCK INHIBIT signal is low. Counter advancement via

the clock line is inhibited when the CLOCK INHIBIT signal is high. A

high RESET signal clears the counter to its zero count. Use of the Johnson

counter configuration permits high-speed operation, 2-input decode-gating

and spike-free decoded outputs. Anti-lock gating is provided, thus

assuring proper counting sequence. The decoded outputs are normally low

and go high only at their respective decoded time slot. Each decoded

output remains high for one full clock cycle. A CARRY-OUT signal

completes one cycle every 10 clock input cycles.

DW SUFFIX

SOIC

ORDERING INFORMATION

KK4017BN Plastic

KK4017BD SOIC

T_A= -55° to 125° C for all packages

•

Operating Voltage Range: 3.0 to 18 V

Maximum input current of 1 µA at 18 V over full package-temperature

range; 100 nA at 18 V and 25°C

•

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

PIN ASSIGNMENT

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

LOGIC DIAGRAM

FUNCTION TABLE

Clock

Enable

Reset Output State

no change

reset counter

Q0=H, Q1-Q9=L,

C0=H

Advance to next

state

no change

PIN 16 =V_CC

PIN 8 = GND

Advance to next

state

Carry Out=H for Q0,Q1,Q2,Q3 or Q4=H

Carry Out = L otherwise, X=don’t care

12 3 4 5 6 7

中文翻译

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