KK4029B

更新时间： 2024-09-17 03:48:07

品牌	Logo	应用领域
可天士 - KODENSHI		计数器高压栅
页数	文件大小	规格书
9页	596K
描述
Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

KK4029B 数据手册

TECHNICAL DATA

KK4029B

Presettable Up/Down Counter

High-Voltage Silicon-Gate CMOS

The KK4029B consists of a four-stage binary or BCD-decade up/down

counter with provisions for look-ahead carry in both counting modes. The

inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE),

BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual

JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as

outputs.

A high PRESET ENABLE signal allows information on the JAM

INPUTS to preset the counter to any state asynchronously with the clock.

A low on each JAM line, when the PRESET-ENABLE signal is high,

resets the counter to its zero count. The counter is advanced one count at

the positive transition of the clock when the CARRY IN and PRESET

ENABLE signals are low. Advancement is inhibited when the

CARRY IN or PRESET ENABLE signals are high. The CARRY OUT

signal is normally high and goes low when the counter reaches its

maximum count in the UP mode or the minimum count in the DOWN

ORDERING INFORMATION

KK4029BN Plastic

KK4029BD SOIC

T_A= -55° to 125° C for all packages

mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK

ENABLE. The CARRY IN terminal must be connected to GND when

not in use.

PIN ASSIGNMENT

Binary counting is accomplished when the BINARY/DECADE

input is high; the counter counts in the decade mode when the

BINARY/DECADE input is low. The counter counts up when the

UP/DOWN input is high, and down when the UP/DOWN input is low.

Parallel clocking provides synchronous control and hence faster

response from all counting outputs. Ripple-clocking allows for longer

clock input rise and fall times.

•

Operating Voltage Range: 3.0 to 18 V

Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25°C

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

•

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

LOGIC DIAGRAM

PIN 16=V_CC

PIN 8= GND

12 3 4 5 6 7...9

中文翻译

下载PDF

与KK4029B相关器件

型号	品牌	获取价格	描述	数据表
KK4029BD	KODENSHI	获取价格	Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS
KK4029BN	KODENSHI	获取价格	Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS
KK4030B	KODENSHI	获取价格	Quad Exclusive-OR Gate High-Voltage Silicon-Gate CMOS
KK4030BD	KODENSHI	获取价格	Quad Exclusive-OR Gate High-Voltage Silicon-Gate CMOS
KK4030BN	KODENSHI	获取价格	Quad Exclusive-OR Gate High-Voltage Silicon-Gate CMOS
KK4034B	KODENSHI	获取价格	8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register High-Voltage Silic
KK4034BDW	KODENSHI	获取价格	8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register High-Voltage Silic
KK4034BN	KODENSHI	获取价格	8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register High-Voltage Silic
KK4040B	KODENSHI	获取价格	12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS
KK4040BD	KODENSHI	获取价格	12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS