KK4027BN

更新时间： 2024-11-07 03:48:07

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KK4027BN 数据手册

TECHNICAL DATA

KK4027B

Dual JK Flip-Flop

The KK4027B is a Dual JK Flip-Flop which is edge-triggered and

features independent Set, Reset, and Clock inputs. Data is accepted when

the Clock is LOW and transferred to the output on the positive-going edge

of the Clock. The active HIGH asynchronous Reset and Set are

independent and override the J, K, or Clock inputs. The outputs are

buffered for best system performance.

•

Operating Voltage Range: 3.0 to 18 V

Maximum input current of 1 µA at 18 V over full package-temperature

range; 100 nA at 18 V and 25°C

•

Noise margin (over full package temperature range):

ORDERING INFORMATION

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

KK4027BN

Plastic

KK4027BD SOIC

T_A= -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Set Reset Clock

Outputs

Q_n+1Q_n+1

No change

PIN 16 =V_CC

PIN 8 = GND

X = don’t care

Qn+1 = State After Clock Positive Transition

12 3 4 5 6

中文翻译

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