Datasheet > KK4021B

KK4021B

更新时间： 2024-11-07 03:48:07

品牌	Logo	应用领域
可天士 - KODENSHI		移位寄存器高压栅
页数	文件大小	规格书
5页	335K
描述
8-Bit Shift Register High-Voltage Silicon-Gate CMOS

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数据手册

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KK4021B 数据手册

TECHNICAL DATA

KK4021B

8-Bit Shift Register

High-Voltage Silicon-Gate CMOS

The KK4021B is an Edge-Triggered 8-Bit Shift Register (Parallel-to-

Serial Converter) with a synchronous Serial Data Input (D_S), a Clock

Input (CP), an asynchronous active HIGH Parallel Load Input (PL), eight

asynchronous Parallel Data Inputs (P₀-P₇) and Buffered Parallel Outputs

from the last three stages (Q₅-Q₇).

Information on the Parallel Data Inputs (P0-P7) is asynchronously

loaded into the register while the Parallel Load Input (PL) is HIGH,

independent of the Clock (CP) and Serial Data (D_S) inputs. Data present

in the register is stored on the HIGH-to-LOW transition of the Parallel

Load Input (PL).

When the Parallel Load Input is LOW, data on the Serial Data Input

(D_S) is shifted into the first register position and all the data in the register

is shifted one position to the right on the LOW-to-HIGH transition of the

Clock Input (CP).

ORDERING INFORMATION

KK4021BN Plastic

KK4021BDW SOIC

T_A= -55° to 125° C for all packages

•

Operating Voltage Range: 3.0 to 18 V

Maximum input current of 1 µA at 18 V over full package-temperature

range; 100 nA at 18 V and 25°C

PIN ASSIGNMENT

•

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

LOGIC DIAGRAM

FUNCTION TABLE

SERIAL OPERATION:

Q₅

Q₆

Q₇

D_S

t=n+6 t=n+7 t=n+8

n+1

n+2

n+3

Q₅

Q₆

Q₇

PARALLEL OPERATION:

D_S

PL P₅P₆P₇Q₅Q₆Q₇

X = don’t care

D = 1 or 0

PIN 16 =V_CC

PIN 8 = GND

12 3 4 5

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与KK4021B相关器件

型号	品牌	获取价格	描述	数据表
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KK4024BN	KODENSHI	获取价格	7 Stage Ripple-Carry Binary Counter/Divider High-Voltage Silicon-Gate CMOS
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